1Sep 30-Oct 1, 2009EFW I-CDR Instrument Critical Design Review EFW Flight Software Peter R. Harvey 2009 Aug 31 RBSP Radiation Belt Storm Probes RBSP Radiation Belt Storm Probes

2Sep 30-Oct 1, 2009EFW I-CDR Outline Flight Software Overview Flight Software Context Changes Since Preliminary Design Review Detailed Software Design Functional description Structural decomposition Timing Commands and Telemetry Resource Margins Software Verification and Testing Status of Engineering Model Software Development Environment and Support of Flight Operations Backup Materials

3Sep 30-Oct 1, 2009EFW I-CDR Overview Development Plan : RBSP_EFW_SW_001 Heritage : CRRES, Polar, Cluster, THEMIS Language: Z80 Requirements: 185 Level 3 Effort : ~14100 SLOC in 22 modules Test Platform: ETU Quality : Integrated with Flight Development Major Functional Requirements: Command Reception & Distribution Real-Time Data Collection and Playback On-Board Evaluation for Burst Triggering Burst Data Collection and Playback Sine-Wave Fits of E-Field & Mag Signals Spacecraft Potential Calculation Data Compression Boom Deployment Control

4Sep 30-Oct 1, 2009EFW I-CDR Context PROCESSOR CPU: IP Z80 Clock: 16 MHz RAM: 56 K EEPROM: 128K SRAM: 64 K SDRAM: 256M FLASH: 32G A/D : 16-Bit

5Sep 30-Oct 1, 2009EFW I-CDR CSCI’s

6Sep 30-Oct 1, 2009EFW I-CDR CSCI’s

7Sep 30-Oct 1, 2009EFW I-CDR Changes Since PDR Results of trade studies : None required Major changes in software requirements : None Major changes in ICDs : None Major changes in top-level design : None Peer reviews since PDR : FSW peer Sept 3, 2009 No Action Items Major open technical, programmatic issues, or risks : None Status of Action Items

8Sep 30-Oct 1, 2009EFW I-CDR Design FSW Major Modules

9Sep 30-Oct 1, 2009EFW I-CDR Boot/Initialization Hardware Reset Power-On Watchdog Reset (3-seconds) Reset Sequence Copies PROM into RAM Initializes Data area to zero Issues Initialization Calls to Each Module Starts in Safe Mode (low power) Begins Engineering Telemetry (1-sec) Checksums EEPROM programs (4 of them) Selects first-program with Good Checksum Waits Until 10 seconds elapsed time Runs Selected Program

10Sep 30-Oct 1, 2009EFW I-CDR Modes & Enables FSW Modes Safe – Minimal Power Configuration, Resets to Safe Normal - FLASH Memory Allowed, Deployment Disabled Engineering - Deployments Allowed

11Sep 30-Oct 1, 2009EFW I-CDR Timing Dual Time Bases Required (Spacecraft & Instrument) S/C & Instrument Both Provide 1Hz Ticks DCB Actel Latches Time Difference Between Ticks FSW Adds Time Offset into Packet Time Accuracy of sec Src: RBSP_EFW_FSW_004_Analyses.xls TIME. See also RBSP_EFW_TN_015B.doc

12Sep 30-Oct 1, 2009EFW I-CDR Timing Interrupts 256 Hz Interrupt Process Distributes CPU Time per Table Basic ¼ second table repeats 4Hz –CMD gets 32 Hz –DFB Packet gets 128 & 16 Hz, etc. Guarantees <4 msec response to events Background measures 3.5%

13Sep 30-Oct 1, 2009EFW I-CDR Sectoring Spin Sectoring (ACS) Maintain 8-bit accurate spin phase (1.41 degrees) Detect Sun Pulse and Determine Spin Period Scientific Operation required for Spin Rates of 4-6 RPM Capable of Handling Spin Rates of 3-15 RPM Provide phase to FIT to take E&B data every 1/32 of a spin Provide phase to BEB module to trigger sweeps Provide phase to SCI to calculate spacecraft potential.

14Sep 30-Oct 1, 2009EFW I-CDR Deployments Motor Deployment DEP Module Controls SPB and AXB Deployment Motors Deployment Enable Must be Commanded On Same module as CRRES (2), Polar(4), Cluster(16), THEMIS(5) Will Deploy One Axis at a Time (in Pairs) or One at a Time Monitors Turns Clicks (SPB, AXB click rates = clicks/sec) Fail-Equal Strategy : Always Keeps Boom Lengths within 2 Clicks Pauses a Motor on a Faster Boom and Waits for Slower Boom Operates at 16 Hz (8 Hz/boom) Deployment Actuators Deployment Enable Must be Commanded On SPB Doors are Released by.25 to.50 seconds of SMA Power AXB Doors are Released by secs of SMA Power AXB Booms are Released by secs of SMA Power Doors are Independently Controlled Operates at 16 Hz

15Sep 30-Oct 1, 2009EFW I-CDR Data Collection DMA Channels are Assigned to Each DFB Data Source Based upon DFB settings, FSW determines packet rate and length FSW Writes SDRAM Destination Addresses into Each Controller DMA Addresses are Double-Buffered to Eliminate Gaps FSW calculates the end of the Interval and raises SwapEnable FSW writes Headers for Each Packet as it is produced Operates at 128Hz (6 Fast Channels), 16 Hz (7 Slow channels) Data Collection Rates Peak Input Rate of 8 MHz Min Length 2 KB for raw data packets Peak Packet Rate of 512 Packets/sec in software design Performance Measurement (nom 260 pps) : 2.1% CPU

16Sep 30-Oct 1, 2009EFW I-CDR Data Analysis On Board Data Analysis – E & B Spin Fits Spin Fit Calculations are Performed on DFB data bit data points are taken at Equal Angles and Stored in Array Spin Fit Reduces 32 samples to Offset, Sine & Cosine terms

17Sep 30-Oct 1, 2009EFW I-CDR Data Analysis On Board Data Analysis – E & B Spin Fits Spin Fit Matrix Results are A, B, C, Sigma (floating point), N (1 byte) Fast Flt Point = 1 sign bit, 7 exponent bits, 16 mantissa bits Each fit time tagged in MET (4 seconds, 2 subseconds) Each Spin Generates = 32 bytes Spin Packet is 8 Spins or 208 bytes Performance: Fit Requires ~720,000 cycles (~43 msec est., 35 measured) Angular Error at 6 RPM (worst case) is +/- 0.5 degrees (sampling)

18Sep 30-Oct 1, 2009EFW I-CDR Data Storage Solid State Recording SDRAM Hardware 256 MB Capacity EDAC Scrubbing EDAC Uses upper 50MB DMA-Channel Operable Quadword Addressable KB Packets FSW Functions Buffers Science Survey Packets to Telemetry Buffers Engineering (Spin Fit) Packets to Telemetry Buffers Burst1 Science Packets out to FLASH (0.1 Mbps) Buffers Burst1 Science Packets back from FLASH (0.003) Mbps Collects Burst2 Science Packets (3.1 Mbps)

19Sep 30-Oct 1, 2009EFW I-CDR Data Storage Solid State Recording FLASH Hardware 32 GB Capacity EDAC Enabled Write/Read DMA-Channel to/fm SDRAM Block Addressable 2^18 128KB Blocks Each Block has 2K extra bytes EDAC Bad-Block-Indicator Erase Count FSW Functions Stores/Retrieves Burst1 Science Blocks (32 4K packets) Circular Memory with Separate Read & Write Ptrs Memory mapping at the ½ GB level (64 segments) Playback Commanded by Block# and Length Storage for 64 Playback requests at a time Both Read/Write Block pointers Telemetered at 1Hz Ground S/W keeps MET to Block# relationship FSW_004_ANALYSES.XLS FMAP : FLASH Virtual-to-Physical Memory Map

20Sep 30-Oct 1, 2009EFW I-CDR Data Evaluation Burst Trigger Calculation FSW calculates how “good” the data is being collected in Burst1 and Burst2 Uses same formula, different factors for Instrument-Shared-Data FSW collects data from several sources into Table 5 DFB Filter Data (Internal data set “x42”) (13x4 bytes) APID 100 Shared Data (EMF, ECT, RBS) Ground command for Conjunction value (“CCC”) FSW Uses Uplink Table 1 for weights & thresholds FSW Calculates B1, B2 and ExtFn at 4Hz FSW Determines calculates requests in ISDM: If value exceeds EXT_REQ_THR and EXT_REQ_ENA is 1, then a request is raised. ISDM is calculated and sent at 1Hz

21Sep 30-Oct 1, 2009EFW I-CDR Data Compression Compression Selected packet is compressed using 16-bit Delta-Modulator v2 DFB packets contain header info on how many waveforms are inside DFB packets have 1-10 waveforms Each waveform cut into 32-sample blocks Result is 1 raw 16-bit sample, 31 deltas The Width of the deltas is determined and the deltas are packed up Packet compression time shown below for varying widths: Required : 12 kbps output Measured: [w=15]: 620 kbps [w= 1] : 97 kbps

22Sep 30-Oct 1, 2009EFW I-CDR Commands and Telemetry Allocation = 285

23Sep 30-Oct 1, 2009EFW I-CDR Commands Command Blocks DMA Input in Blocks containing multiple Command Packets FSW Checks/Decodes each Packet in the Block FSW Handles APIDs 100, 260 and 261 APID 100: Time and Status (1Hz) Provide S/C MET, Status EFW Recorder Status (255 = 100% full) Shared Data from ETC, EMFISIS (inc. Mag Gain), RBSPICE APID 260: Command Strings Contain Strings of 16-bit Command Codes Command Codes are Entered into 256-command FIFO Command Codes are Executed Under Interrupt at 32 Hz APID 261:Memory Loads Memory Load Packets Include Address and Length Variable Size Loads up to 250 bytes per packet If EEPROM is ON & enabled, can directly load EEPROM

24Sep 30-Oct 1, 2009EFW I-CDR Engineering Telemetry Housekeeping Telemetry APIDs A Contain Software Generated Data Commandable Rate Controls per packet type Not Compressed (S/C & GSE do not need decompressors) APID 262: IDPU Critical Housekeeping (1Hz) Provide EFW_Shared Status Provide EFW Critical Housekeeping Currents Not Normally Saved in S/C SSR or telemetered APID 263: FAST Digital Status (1/2 Hz, 160 bps) Provide EFW Fast Digital Status Packet length: 40 bytes APID 264: IDPU Analog Status (1/16Hz, 18 bps) Provide EFW Analog Status Packet est. 36 bytes

25Sep 30-Oct 1, 2009EFW I-CDR Engineering Telemetry ADID 265: BEB Analog (post-sweep) Provides Boom Electronics Board readback Fixed Length: 40 bytes APID 266: Memory Dump (on demand) Provides Ability to Verify Memory Loads, Parameters Commandable Length up to 128 bytes of data APID 267: Engineering HSK (1/8 secs, 96 bps) Provide Slower Engineering Data, Command Feedback Length : 96 bytes APID 268: Event Log (after N events) Provide Event telemetry (and Errors) Commandable Number of Events to store (N = 1 to 16)

26Sep 30-Oct 1, 2009EFW I-CDR Engineering Telemetry APID 269: Spin-Fit (1/96 secs, 18 bps) Provide E&B Analyzed Data Spin-Based Data = 8 Spins/Packet Length = 208 bytes APID 26A: Space Weather (1/spin) Provide EFW Spin Fit Result Provide Spacecraft Potential Not Normally Saved in S/C SSR or telemetered Length = 28 bytes

27Sep 30-Oct 1, 2009EFW I-CDR Science Telemetry Telemetry Packet Selection Select Engineering, Survey, Burst1 or Burst2 if enabled Fixed Priority is Engineering, Survey, Burst1 and Burst2 Selected packet is compressed by CMP module Buffer pointers are moved enabling telemetry when TM module is able Serial Telemetry DMA Management Provides Mixing of SOH Housekeeping and Science Data Implements 50 msec “telemetry interface window” before 1 PPS FSW Will Not Start a Transmission Beyond 0.5 sec (0.4s longest pkt) FSW maintains a bit rate monitor to regulate packet output FSW transmits APID 262 (Health & Status) every second FSW transmits other HSK packets (APID 26x) when ready. FSW transmits 1 RT Science packet if ready FSW transmits 1-2 Burst packets when bit rate < Allocation (12k def.) Status Successful TM stress-testing at up to 60 kbps

28Sep 30-Oct 1, 2009EFW I-CDR CPU Resources CPU Performance Based upon 16.8 MHz processor Measurements made on RBSP ETU DCB Calculations in RBSP_EFW_FSW_004_Analyses.xls Using Worst Case Compressable Data (10:1 compression) Nominal Spin Rate (12 seconds) for Spin Fits

29Sep 30-Oct 1, 2009EFW I-CDR Memory Resources PROM/EEPROM PROM Functions EEPROM Load Uplink Support L&EO Functions EEPROM/Uplink One-Time Events Test Programs Initialization Params Science Upgrades RESOURCE NEEDS 45% PROM 47% RAM 3% EEPROM

30Sep 30-Oct 1, 2009EFW I-CDR Memory Resources EEPROM Map

31Sep 30-Oct 1, 2009EFW I-CDR Memory Resources SRAM Requirements Functions Holds ~15K Code Image in RAM Variables ~12K Total Required of appx 27K SRAM Provided 56K Directly Addressable 128K Page Addressable

32Sep 30-Oct 1, 2009EFW I-CDR Integration & Test FSW Development DCB BB, ETU & GSE used for development FSW Developed in 4 phases Verification Matrix Provides Status of Requirements Comprehensive Performance Test on ETU Load into Flight Systems Joins IDPU Test Flow and Quality reporting FSW Maintenance IDPU ETU & GSE Maintained in Flight Configuration Verify command uploads prior to uplink Anomaly resolution

33Sep 30-Oct 1, 2009EFW I-CDR Verification FSW Verification RBSP_EFW_FSW_002_Tables.xls tracks requirement flows Development status, test overview and procedure name

34Sep 30-Oct 1, 2009EFW I-CDR Verification FSW Verification Status Summary Table tracks requirement test status All inspections and analyses completed

35Sep 30-Oct 1, 2009EFW I-CDR To Be Done Items TBDs Development Increase HSK & DEP module frequencies for AXB deployment ICD related items DFB initial configuration & FSW initial configuration should match FSW generates proposed ISDM format but this format is not in any ICD Format of ECT, RBS, EMF burst trigger data to EFW is TBD. Uplinkable Scripts to be defined Space allocated for up to 16 in PROM and more in EEPROM Verification at the Box & Instrument levels GSE/SOC Flash Memory “MET-to-Block” data management GSE/SOC Decompression Software LVPS Control – TBD BEB Sweeps – TBD DFB Sol1, Spec and Xspec Data - TBD Boom Door Opening & Wire Deployment – TBD

36Sep 30-Oct 1, 2009EFW I-CDR Development & Flight Development Environment ETU Data Controller Board (DCB) PROM Simulator ASM85/LINK85/MAKE GSE Laptop with GSEOS, Spacecraft mini-emulator GSE Screens and Python Scripts Flight Support Engineering Model IDPU & 2 Booms ASM85/LINK85/MAKE for Uplink software GSE Laptop with GSEOS, Spacecraft emulator Updated Screens and Python Scripts