© 2004 Xilinx, Inc. All Rights Reserved Implemented by : Alon Ben Shalom Yoni Landau Project supervised by: Mony Orbach High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering Characterization Presentation Spring 2007

© 2004 Xilinx, Inc. All Rights Reserved Agenda Background Platforms & Devices Project Goals Stages of the project Schedule

© 2004 Xilinx, Inc. All Rights Reserved Background What is a CCD camera ? A silicon based camera – using the photoelectric principal Why using a CCD camera ? Cheap high quality solution for video image applications CCD - Charge-Coupled Device

© 2004 Xilinx, Inc. All Rights Reserved Background (Cont.) What is Virtex-II Pro ? Virtex-II Pro,supported by XUP board, is a complete FPGA system which includes up to 2GB DDR SDRAM, 10/100 Ethernet MAC/PHY, High/Low speed expansion connectors, USB2, PS/2 for mouse/keyboard and a serial port.

© 2004 Xilinx, Inc. All Rights Reserved Platforms & Devices

© 2004 Xilinx, Inc. All Rights Reserved M4088 is a ¼ ” Monochrome digital camera The M4088 digital camera is based on OV5017 CCD chip manufactured by OmniVision. Chip Interface : M4088 camera module. M4088

© 2004 Xilinx, Inc. All Rights Reserved Camera Highlights Low power consumption (< 100mW ). Array size 384*288 pixels. Built in A/D output – 8 bit pixel resolution. Programmable exposure setting. Single 5-volt supply operation for analog and 5/3.3 volts for digital.

© 2004 Xilinx, Inc. All Rights Reserved Project Goals Implementation By an adapter that convert voltage/current to/from the camera and the XUP board. Capture a single frame and forward it to DDR SDRAM using Virtex II PRO.

© 2004 Xilinx, Inc. All Rights Reserved M4088 ov5017 External power supply Biases and data to/from adapter (from there to XUP) Adapter XUP Vertex II PRO Biases and data to/from adapter (from there to the camera)

© 2004 Xilinx, Inc. All Rights Reserved Stages of the Project Dive in spec of Virtex II pro & CCD camera Get familiar with development tools (EDK, VHDL…) Submit mid term report Implementing the connection between the devices Presentation of the adapter Submit final report

© 2004 Xilinx, Inc. All Rights Reserved Schedule 29 May – middle term report – include pin to pin scheme 28 June - perform first tests to the adapter 29 June – Presentation of the Adapter