Chapter 5 2-23-09

Read pages 311-337 much useful information such as common gates on page 329 Open collector Schmitt trigger

Programmable Logic Arrays (PLAs) Any combinational logic function can be realized as a sum of products. Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. n inputs AND gates have 2n inputs -- true and complement of each variable. m outputs, driven by large OR gates Each AND gate is programmably connected to each output’s OR gate. p AND gates (p<<2n The number of minterms)

Example: 4x3 PLA, 6 product terms (Programmed by blowing fuses)

PLD’s – PLA’s page 337-345 Implement BCD to Excess-3. See page 49.

BCD to Excess-3 via PLA BCD EXCESS-3 I1 I2 I3 I4 O1 O2 O3 O4 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 O1 = (5,6,7,8,9;d,10,11,12,13,14,15) = I1’I2I3’I4 + I1’I2I3I4’+I1’I2I3I4 +I1I2’I3’I4’+ I1I2’I3’I4 O2 = (1,2,3,4,9;d,10,11,12,13,14,15) = I1’I2’I3’I4+ I1’I2’I3I4’+ I1’I2’I3I4+ I1I2’I3’I4’+ I1I2I3’I4’ O3 = (0,3,4,7,8;d,10,11,12,13,14,15) = I1’I2’I3’I4’+ I1’I2’I3I4+ I1’I2I3’I4’+ I1’I2I3I4+ I1I2’I3’I4’ O4 = (0,2,4,6,8;d,10,11,12,13,14,15) = I4’

Some product terms

PLA Electrical Design See Section 5.3.5 -- wired-AND logic

Programmable Array Logic (PALs) How beneficial is product sharing? Not enough to justify the extra AND array PALs ==> fixed OR array Each AND gate is permanently connected to a certain OR gate. Example: PAL16L8

10 primary inputs 8 outputs, with 7 ANDs per output 1 AND for 3-state enable 6 outputs available as inputs more inputs, at expense of outputs two-pass logic, helper terms Note inversion on outputs output is complement of sum-of-products newer PALs have selectable inversion

Decoders General decoder structure Typically n inputs, 2n outputs 2-to-4, 3-to-8, 4-to-16, etc.

Binary 2-to-4 decoder Note “x” (don’t care) notation. Y(I1, I0)

2-to-4-decoder logic diagram Y(I1, I0)

MSI 2-to-4 decoder Y(B, A) Input buffering (less load) NAND gates (faster) Y(B, A)

Decoder Symbol Y(B, A)

Complete 74x139 Decoder Y(B, A)

More decoder symbols

3-to-8 decoder Y(C, B, A)

74x138 3-to-8-decoder symbol Y(C, B, A)

Decoder cascading Y(C, B, A) 4-to-16 decoder

More cascading 5-to-32 decoder

Decoder applications Microprocessor memory systems selecting different banks of memory Microprocessor input/output systems selecting different devices Microprocessor instruction decoding enabling different functional units Memory chips enabling different rows of memory depending on address Lots of other applications

Tri-state drivers

Three-state buffers Output = LOW, HIGH, or Hi-Z. Can tie multiple outputs together, if at most one at a time is enabled.

Different flavors

Only one Y can be low at a time.

Three-state drivers

Typical application of tri-state drivers – input port. INSELn’s are a function of Address signals. They may be obtained external to the microprocessor using a decoder (74LS138).

Three-state transceiver Typical application – connected to microprocessor data buss to provide sufficient current drive for multiple memory and I/O (input and output) ports.

Multiplexers – many inputs to one output.

74x151 8-input multiplexer

74x151 truth table

Logic design using multiplexer.

m W X Y Z F n Dn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Y X W

Equality Comparators 1-bit comparator 4-bit comparator EQ_L

Adders Basic building block is “full adder” 1-bit-wide adder, produces sum and carry outputs Truth table: X Y Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Full Adder X Cout 1 Cin Y X S 1 Cin Y

Full-adder circuit Delay X, Y, Cin to Cout = 2. Delay X, Y to S = 2. Delay Cin to S = 1.

Ripple adder Speed limited by carry chain Delay X, Y, Cin to Cout = 2. Delay X, Y to S = 2. Delay Cin to S = 1. Speed limited by carry chain Faster adders eliminate or limit carry chain 2-level AND-OR logic ==> 2n product terms 3 or 4 levels of logic, carry lookahead (see book). Two’s complement subtraction: Invert and add 1.

Multipliers 8x8 multiplier

Full-adder array

Faster carry chain

Read-Only Memories

Why “ROM”? Program storage Boot ROM for personal computers Program for embedded application storage for embedded systems. Actually, a ROM is a combinational circuit, basically a truth-table lookup. Can perform any combinational logic function Address inputs = function inputs Data outputs = function outputs

Logic-in-ROM example

4x4 multiplier example

Internal ROM structure PDP-11 boot ROM (64 words, 1024 diodes)

Two-dimensional decoding ?

Typical commercial EEPROMs

EEPROM programming Apply a higher voltage to force bit change E.g., VPP = 12 V On-chip high-voltage “charge pump” in newer chips Erase bits Byte-byte Entire chip (“flash”) One block (typically 32K - 66K bytes) at a time Programming and erasing are a lot slower than reading (milliseconds vs. 10’s of nanoseconds)

Microprocessor EPROM application