EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic July 30, 2002

EE141 © Digital Integrated Circuits 2nd Wires 2 The Wire schematics physical

EE141 © Digital Integrated Circuits 2nd Wires 3 Interconnect Impact on Chip

EE141 © Digital Integrated Circuits 2nd Wires 4 Wire Models All-inclusive model Capacitance-only

EE141 © Digital Integrated Circuits 2nd Wires 5 Impact of Interconnect Parasitics  Interconnect parasitics  reduce reliability  affect performance and power consumption  Classes of parasitics  Capacitive  Resistive  Inductive

EE141 © Digital Integrated Circuits 2nd Wires 6 Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel

EE141 © Digital Integrated Circuits 2nd Wires 7 INTERCONNECT

EE141 © Digital Integrated Circuits 2nd Wires 8 Capacitance of Wire Interconnect

EE141 © Digital Integrated Circuits 2nd Wires 9 Capacitance: The Parallel Plate Model

EE141 © Digital Integrated Circuits 2nd Wires 10 Permittivity

EE141 © Digital Integrated Circuits 2nd Wires 11 Fringing Capacitance

EE141 © Digital Integrated Circuits 2nd Wires 12 Fringing versus Parallel Plate

EE141 © Digital Integrated Circuits 2nd Wires 13 Interwire Capacitance

EE141 © Digital Integrated Circuits 2nd Wires 14 Interwire Capacitance (Process Data)

EE141 © Digital Integrated Circuits 2nd Wires 15 DB and SB Capacitance

EE141 © Digital Integrated Circuits 2nd Wires 16 Gate Capacitance

EE141 © Digital Integrated Circuits 2nd Wires 17 INTERCONNECT

EE141 © Digital Integrated Circuits 2nd Wires 18 Wire Resistance

EE141 © Digital Integrated Circuits 2nd Wires 19 Interconnect Resistance

EE141 © Digital Integrated Circuits 2nd Wires 20 Dealing with Resistance  Selective Technology Scaling  Use Better Interconnect Materials  reduce average wire-length  e.g. copper, silicides  More Interconnect Layers  reduce average wire-length

EE141 © Digital Integrated Circuits 2nd Wires 21 Sheet Resistance

EE141 © Digital Integrated Circuits 2nd Wires 22 Sheet Resistance (Process Data)

EE141 © Digital Integrated Circuits 2nd Wires 23 Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

EE141 © Digital Integrated Circuits 2nd Wires 24 InterconnectModeling

EE141 © Digital Integrated Circuits 2nd Wires 25 The Lumped Model

EE141 © Digital Integrated Circuits 2nd Wires 26 The Lumped RC-Model The Elmore Delay

EE141 © Digital Integrated Circuits 2nd Wires 27 The Ellmore Delay RC Chain

EE141 © Digital Integrated Circuits 2nd Wires 28 Wire Model Assume: Wire modeled by N equal-length segments For large values of N:

EE141 © Digital Integrated Circuits 2nd Wires 29 The Distributed RC-line

EE141 © Digital Integrated Circuits 2nd Wires 30 Step-response of RC wire as a function of time and space

EE141 © Digital Integrated Circuits 2nd Wires 31 RC-Models

EE141 © Digital Integrated Circuits 2nd Wires 32 Driving an RC-line

EE141 © Digital Integrated Circuits 2nd Wires 33 Design Rules of Thumb  rc delays should only be considered when t pRC >> t pgate of the driving gate Lcrit >>  t pgate /0.38rc  rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC  when not met, the change in the signal is slower than the propagation delay of the wire © MJIrwin, PSU, 2000