CS 312 Computer Architecture Memory Basics Department of Computer Science Southern Illinois University Edwardsville Summer, 2015 Dr. Hiroshi Fujinoki MemoryBasics/000

CS 312 Computer Architecture MemoryBasics/001 The problem in memory system “An improvement rate of 60%/year in microprocessor performance, while the access time to DRAM has been improving at less than 10%/year” “The Gap between Processor and Memory Speeds” by Carlos Carvalho Throughput

What is “memory” in a computer system? (1) Memory is a collection of capacitors that can hold electricity (3) Memory is referenced by ROW address and COLUMN address (2) Condensers are organized as an N  N matrix (4) Two types of memory: - Dynamic RAM (DRAM) and Static RAM (SRAM) (5) SRAM is faster (i.e., shorter access latency) than DRAM - SRAM is used for L2 (or L3 cache) CS 312 Computer Architecture MemoryBasics/002

Row Address Column Address Signal Condenser (capacitor) - holds electricity for ms. Internal structure of typical DRAM one bit = CS 312 Computer Architecture MemoryBasics/003

 Linear Address (00000~FFFFF)  Column Address  Memory Precharge Memory access architecture for DRAM CPU Memory Controller  Data Out  Data  Row Address CS 312 Computer Architecture MemoryBasics/004

(1) CPU sends memory access request to the memory controller (2) The memory controller issues RAS (Row Access Strobe) (3) The memory controller issues CAS (Column Access Strobe) (4) Memory chip waits for stabilized (5) Memory chip responds Time (6) PreCharge CS 312 Computer Architecture MemoryBasics/005

CPU registers Cache memory within a CPU (Level-1 Cache) Cache memory on a motherboard (Level-2 Cache) Main memory Memory Hierarchy Hard drive Fastest Slowest CS 312 Computer Architecture MemoryBasics/006

CPU registers Cache memory within a CPU (Level-1 Cache) Cache memory on a motherboard (Level-2 Cache) Main memory Memory Hierarchy Hard drive Fastest Slowest Highest Cost Lowest Cost We have a trade-off problem “Cost” = $$$ amount for each byte CS 312 Computer Architecture MemoryBasics/007

Level-1 Cache (Part 1 – Intel’s i486) The L1-cache in i486 CS 312 Computer Architecture MemoryBasics/008

Level-1 (L1) Cache Level-1 Cache (Part 2 – Intel’s Pentium 4) CS 312 Computer Architecture MemoryBasics/009

(1) (2)(3) (1) (2)(3) (1) (2)(3) (1) (2)(3) (1) RAS Strobe (Issuing Row Address) (2) CAS Strobe (Issuing Column Address) (3) Data Out/In (Data Read/Write) Memory Pipelining - Concept CS 312 Computer Architecture MemoryBasics/010

Row Strobe Memory Pipelining Column Strobe Output Time Memory Chip A memory access technique used in SDRAM Access latency for each memory chip is still slow (40-60 ns) CS 312 Computer Architecture MemoryBasics/011

One memory bank Row Address Module Selector Memory Inter-leave (address) MOD 3 = 0 (address) MOD 3 = 1 (address) MOD 3 = 2 Column Address CS 312 Computer Architecture MemoryBasics/012