Lecture 3 Chap 4 Types Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University

Types: VHDL is a strongly-typed language Eight classes of types in VHDL: classsynthesisable Enumeration typesY Integer typesY Floating point typesN Physical typesN Array typesY Record typesY Access typesN File typesN

Standard Types: Predefined types in standard package: Type classsynthesisable boolean enumeration typeY bit enumeration typeY characterenumeration type Y severity_level enumeration type N integer integer typeY natural subtype of integerY positivesubtype of integerY realfloating point typeN timephysical typeN stringarray of charY bit_vectorarray of bitY

Std_logic_1164 Types: Predefined types in std_logic_1164 package: Type classsynthesisable std_ulogic enumeration typeY std_logicsubtype of std_ulogicY std_ulogic_vector array of std_ulogicY

Standard Operators Values, signals and variables of a type can be combined in expressions using operators VHDL operators: VHDL’93 in italic font booleannot, and, or, nand, nor, xor, xnor comparison=, /=,, >= shifting sll, srl, sla, sra, rol, ror arithmetics+, s-, +, -, *, /, mod, rem, abs, ** concatenation &

Type: bit bit is the built-in logical type. type bit is (‘0’, ‘1’) -- bit has two values. Operators: booleannot, and, or, nand, nor, xor, xnor comparison=, /=,, >= boolean operator: a xor b ==> bit type comparison operator: a = b ==> boolean type

Type: boolean boolean is the built-in comparison type. type boolean is (false, true) -- boolean has two values. Operators: booleannot, and, or, nand, nor, xor, xnor comparison=, /=,, >= boolean operator: a xor b ==> boolean type comparison operator: a = b ==> boolean type Hardware mapping: boolean ==> a single wire Example: A. a = b ==> a nxor b (a, b are type of boolean) B. a = 0 and = b=1 (a, b are 4-bit numbers) see pp 42.

Integer Type Integer is the built-in numeric type. type integer is range to ; Operator: comparison=, /=,, >= arithmetics+, s-, +, -, *, /, mod, rem, abs, ** 8-bit arithmetic integer type: (used-defined integers) type short is range -128 to 127 ; You can not mix type integer and short. The new type (short) assumes the operators of Integer Hardware mapping: a bus of wire

Integer Subtype Integer subtypes: A. subtype natural is integer range 0 to integer’high B. subtype positive is integer range 1 to integer’high. integer’high is the highest value of type integer. 4-bit subtype of integer: subtype nat4 is natural range 0 to 15. Hardware mapping: a bus of wire

Integer Subtype w, x, y, z are 4-bit unsigned number. W <= x - y + z add signed bit to unsigned data

Enumeration Types An enumeration type is a type composed of a set of literal values. Examples: A. type state is (main_green, main_yellow, farm_green, farm_yellow); B. type mvl4 is (‘X’, ‘0’, ‘1’, ‘Z’); C. type boolean is (false, true); D. type bit is (‘0’, ‘1’); No arithmetic operation on enumeration types.

Multi-valued logic types standard type called std_logic is a nine-value logic type std_logic is not part of VHDL language, but it is in IEEE standard extension to the language under standard number You must include the following lines to use std_logic Library ieee; use ieee.std_logic_1164.all;

Multi-valued logic types type std_ulogic is ( ‘U’, -- Uninitialized ‘X’, -- Forcing unknown ‘0’, -- Forcing 0 ‘1’, -- Forcing 1 ‘Z’, -- High imepdance ‘W’, -- Weak unknown ‘L’, -- Weak 0 ‘H’, -- Weak 1 ‘-’, -- Don’t care );

Records A record is a collection of elements. Each of the elements can be of any constrained type or subtype Example: type complex is record Read : integer; imag : integer; end record; signal a, b, c: complex; operator: comparison =, /=

Records Access an element of a record a.real <= 0; a 0, imag =>0); a <= (0,0); (r,i) <= a; r <= a.real i <= a.imag

Arrays An array is a collection of same-type elements An array can be unconstrained or constrained. Unconstrained array: size of the array is unspecified. Constrained array: size and index type are given. Examples: type std_logic_vector is array (natural range<>) of std_logic; signal a: std_logic_vector (3 downto 0); (3 downto 0) is called a descending range: first (left) element is 3 and the last (right element) is 0. Bus: descending range

Array Subtype slv4 is std_logic_vector (3 downto 0); signal a: slv4; signal up: std_logic_vector (1 to 4); signal down: std_logic_vector(4 downto 1); down <= up; down(4) <= up(1); down(3) <= up(2); down(2) <= up(3); down(1) <= up(4);

Array down(1 downto 0) <= down(4 downto 3); down ’1’, 2=>’0’, 1=>’0’, 0 =>’0’); down ’1’,2|1|0 => ‘0’); down ’1’,2 downto 0 => ‘0’); down ’1’, others => ‘0’); down <= (‘1’, ‘0’, ‘0’, ‘0’);

Array x <= B”0000_0000_1111”; x <= O”00_17”; x <= X”00F”; signal a,b : std_logic_vector(7 downto 0); signal z: std_logic_vector(15 downto 0); … z <= a & b;

Attributes Attributes are a device for eliciting information from a type or from the values of a type. Attributes of Integer and Enumeration types: type’lefttype’right type’hightype’low type’pred(value)type’succ(vaule) type’leftof(value)type’rightof(value) type’pos(value)type’val(value)

Attributes Example type state is (green, yellow, red); type short is range -128 to 127; type backward is range 127 to -128; state’left --> greenstate’right --> red short’left-->-128short’right -->127 backward’left--> 127 backward’right-->-128 state’low--> state’high--> short’low-->short’high--> backward’low-->backward’high-->

Attributes Example type state is (green, yellow, red); type short is range -128 to 127; type backward is range 127 to -128; state’pos(green) --> 0state’val(2) --> red state’pred(yellow) -->green state’succ(yellow) -->red short’pred(0) --> -1short’leftof(0) --> -1 backward’pred(0) -->backward’succ(0) --> state’succ(red) --> error

Attributes Array attributes: size, range, index a‘left, a’right, a‘low, a.high, a’range, a‘reverse_length, a’length Example: signal up: std_logic_vector (0 to 3); signal down: std_logic_vector(3 downto 0); up’left --> 0down’left --> 3 up’right --> 3down’right --> 0 up’low --> 0down’low --> 0 up’high --> 3down’high --> 3 sign <= down(down’left);

Attributes Example: signal a: std_logic_vector (3 downto 0); signal b: std_logic_vector(a’range); signal c: std_logic_vector (a’reverse_range); signal c: bit_vector (13 to 24); signal d: bit_vector(c’length-1 downto 0); d <= c;