Presentation is loading. Please wait.

Presentation is loading. Please wait.

The IEEE Libraries And Examples Using Functions. Libraries Using the Library Command VHDL allows libraries defined using: library LibraryName; Here, we.

Published by Modified over 8 years ago

Similar presentations

Presentation on theme: "The IEEE Libraries And Examples Using Functions. Libraries Using the Library Command VHDL allows libraries defined using: library LibraryName; Here, we."— Presentation transcript:

1 The IEEE Libraries And Examples Using Functions

2 Libraries Using the Library Command VHDL allows libraries defined using: library LibraryName; Here, we specify a search path for the compiler to find different functions. Usually, LibraryName refers to a directory name, where different files are stored. For example: library ieee; refers to the VHDL files that are defined by IEEE. To use specific definitions, we will have to know the name of the file where the definition is find. Here, you can use OS find functions to find a file that contains the definitions. Such files are referred to as package files in VHDL. In these files, you can find important VHDL extensions. We should always consider using any function defined by IEEE, and avoid re-defining any function already given by IEEE.

3 Simple Examples Here are some of the best known IEEE packages: std_logic_1164-- basic definitions std_logic_arith-- general arithmetic functions std_logic_signed-- signed arithmetic functions std_logic_unsigned-- unsigned arithmetic functions To use the definitions from a package, we need the general commands: library LibraryName; -- "directory" name use LibraryName.packageName.all; -- function definitions For the basic definitions, we use: library ieee; use ieee.std_logic_1164.all;

4 IEEE Packages math_complex.vhd -- no source code found … math_real.vhd - - no source code found … numeric_bit.vhd -- ΙΕΕΕ file for VHDL synthesis numeric_std.vhd -- ΙΕΕΕ file for VHDL synthesis std_logic_1164.vhd - - basic definitions for digital logic std_logic_arith.vhd -- large collection of arithmetic functions std_logic_signed.vhd -- signed functions for std_logic_vector std_logic_unsigned.vhd -- unsigned functions for std_logic_vector std_logic_misc.vhd - - miscellaneous std_logic_textio.vhd - - text file processing We will explore some of them in detail.

5 Definition of std_ulogic TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); To understand how these work, we will study the and function …

6 Basic Data Types (Ι/ΙΙ) ------------------------------------------------------------------- -- unconstrained array of std_ulogic for use with the resolution function ------------------------------------------------------------------- TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; ------------------------------------------------------------------- -- *** industry standard logic type *** ------------------------------------------------------------------- SUBTYPE std_logic IS resolved std_ulogic; ------------------------------------------------------------------- -- unconstrained array of std_logic for use in declaring signal arrays ------------------------------------------------------------------- TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

7 Basic Data Types (ΙΙ/ΙΙ) ------------------------------------------------------------------- -- common subtypes ------------------------------------------------------------------- SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1') SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z') SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1') SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')

8 Basic Functions For std_ulogic FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01; FUNCTION "not" ( l : std_ulogic ) RETURN UX01;

9 Basic Functions for Vectors ------------------------------------------------------------------- -- vectorized overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; function "xnor" ( l, r : std_logic_vector ) return std_logic_vector; function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector; FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;

10 Rising and Falling Edges for the Clock ------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;

11 A Simple Example Function: "and" TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | ); -- Note that the outputs are only: U, X, 0, 1. -- L and 0 force the output to be 0. -- A 1-input copies the input to the output, replacing with X. FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (and_table(l, r)); -- note the use of the table! END "and";

12 The STD_LOGIC_ARITH Package -- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --Package name: STD_LOGIC_ARITH Purpose: A set of arithemtic, conversion, and comparison functions for SIGNED, UNSIGNED, SMALL_INT, INTEGER, STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. package std_logic_arith is type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; subtype SMALL_INT is INTEGER range 0 to 1; function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; function "+"(L: SIGNED; R: SIGNED) return SIGNED;

13 Examples of Simple Functions for UNSIGNED Inputs function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; function "+"(L: UNSIGNED) return UNSIGNED; function "ABS"(L: SIGNED) return SIGNED; function "*"(L: UNSIGNED; R: SIGNED) return SIGNED; function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN; function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;

14 Functions for Conversions and Shifts function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED; function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED; function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED; function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED; function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR; function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR; function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR; function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR;

15 Arithmetic Functions function mult(A,B: SIGNED) return SIGNED; function mult(A,B: UNSIGNED) return UNSIGNED; function plus(A, B: SIGNED) return SIGNED; function unsigned_plus(A, B: UNSIGNED) return UNSIGNED; function minus(A, B: SIGNED) return SIGNED; function unsigned_minus(A, B: UNSIGNED) return UNSIGNED; function is_less(A, B: SIGNED) return BOOLEAN; function is_less_or_equal(A, B: SIGNED) return BOOLEAN; function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN; function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN;

16 The STD_LOGIC_SIGNED Package -- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. -- -- All rights reserved. -- --Package name: STD_LOGIC_SIGNED -- function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;

17 The STD_LOGIC_UNSIGNED Package -- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --Package name: STD_LOGIC_UNSIGNED package STD_LOGIC_UNSIGNED is function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;

Download ppt "The IEEE Libraries And Examples Using Functions. Libraries Using the Library Command VHDL allows libraries defined using: library LibraryName; Here, we."

Similar presentations

VHDL in digital circuit synthesis (tutorial) dr inż. Miron Kłosowski EA 309

VHDL in digital circuit synthesis (tutorial) dr inż. Miron Kłosowski EA 309
Introduction to VHDL CLASS MATERIALS EECE 255. Very High Speed Integrated Circuit Hardware Description Language Industry standard language to describe.

Introduction to VHDL CLASS MATERIALS EECE 255. Very High Speed Integrated Circuit Hardware Description Language Industry standard language to describe.
Reconfigurable Computing - Resolution Functions John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound, Western.

Reconfigurable Computing - Resolution Functions John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound, Western.
1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.
Logic Design Fundamentals - 1 Lecture L1.1. Logic Design Fundamentals - 1 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

Logic Design Fundamentals - 1 Lecture L1.1. Logic Design Fundamentals - 1 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.
Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.

Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.
Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.
Comprehensive VHDL Module 6 Types November 2000. 6-2 Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.

Comprehensive VHDL Module 6 Types November Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.
VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.

VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.
Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.

Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.
Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate.

Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate.
VHDL And Synthesis Review. VHDL In Detail Things that we will look at: –Port and Types –Arithmetic Operators –Design styles for Synthesis.

VHDL And Synthesis Review. VHDL In Detail Things that we will look at: –Port and Types –Arithmetic Operators –Design styles for Synthesis.
Programming in VHDL Using Processes. How Processes Run A process is either in suspend mode or is running. For a process to run, there has to be a change.

Programming in VHDL Using Processes. How Processes Run A process is either in suspend mode or is running. For a process to run, there has to be a change.
Introduction to VHDL Multiplexers Discussion D1.1.

Introduction to VHDL Multiplexers Discussion D1.1.
第6章 VHDL NUMBERS, STRINGS, AND EXPRESSIONS 義守大學電機工程學系 陳慶瀚

第6章 VHDL NUMBERS, STRINGS, AND EXPRESSIONS 義守大學電機工程學系 陳慶瀚
Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design.

Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design.
Concordia University 1 Lecture #8 In this lecture we will cover the following material: The standard package, The std_logic_1164  Objects & data Types.

Concordia University 1 Lecture #8 In this lecture we will cover the following material: The standard package, The std_logic_1164  Objects & data Types.
George Mason University Modeling of Arithmetic Circuits ECE 545 Lecture 7.

George Mason University Modeling of Arithmetic Circuits ECE 545 Lecture 7.
Reconfigurable Computing - VHDL - Types John Morris Chung-Ang University The University of Auckland.

Reconfigurable Computing - VHDL - Types John Morris Chung-Ang University The University of Auckland.

Similar presentations

Ads by Google