1. Lecture 5 Chap 6 Package std_logic_arith Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University

2. Introduction The basic set of types provided with VHDL is limited. For example: integer types are limited to 32-bit number no bitwise operation (bitwire and, or,...). No indexing (bit 3:0). Solution: use proprietary packages. De facto standard: std_logic_arith package from Synopsis. There are other competing packages -- standardization is needed.

3. Introduction Two new packages: numeric_std and numeric_bit numeric_std is direct replacement of std_logic_arith numeric_bit is the same package but using type bit as the element type instead of std_logic. IEEE standard (numeric_std and numeric_bit) is not yet in widespread used. numeric_std will be describe in chap 7. Don’t use std_logic_arith and numeric_std at the same time.

4. Std_logic_arith package std_logic_arith represents numeric values as arrays of std_logic. Operator in std_logic_arith: bitwise logic operations, arithmetic operations, and numeric comparison on the same type. directly access individual bits (bus-like operations) To use std_logic_arith packages: library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all;

5. Contents of std_logic_arith two types: type signed is array (natural range <>) of std_logic type unsigned is array (natural range <>) of std_logic Example: signal a: signed(7 downto 0); signal b: unsigned(7 downto 0); Both declarations create 8-bit buses. Signed a: -128 to 127 unsigned b: 0 to 255. Note that std_logic_vector do not have a numeric interpretation.

6. Resize functions resize: truncate or extend values of types signed and unsigned. resize functions: conv_signed and conv_unsigned

7. library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity signed_resize_larger is port(a : in signed(7 downto 0); z : out signed(15 downto 0) ); end; architecture behavior of signed_resize_larger is begin z <= conv_signed(a, 16); end;

8. library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity signed_resize_larger is port(a : in signed(7 downto 0); z : out signed(15 downto 0) ); end; architecture behavior of signed_resize_larger is begin z <= conv_signed(a, z’length); end;

9. library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity unsigned_resize_larger is port(a : in unsigned(7 downto 0); z : out unsigned(15 downto 0) ); end; architecture behavior of unsigned_resize_larger is begin z <= conv_unsigned(a, 16); end;

10. library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity signed_resize_smaller is port(a : in signed(15 downto 0); z : out signed(7 downto 0) ); end; architecture behavior of signed_resize_smaller is begin z <= conv_signed(a, 8); end;

11. Library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity unsigned_resize_smaller is port(a : in unsigned(15 downto 0); z : out unsigned(7 downto 0) ); end; architecture behavior of unsigned_resize_smaller is begin z <= conv_unsigned(a, 8); end;

12. Library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity unsigned_slice is port(a : in unsigned(15 downto 0); z : out unsigned(7 downto 0) ); end; architecture behavior of unsigned_slice is begin z <= a(7 downto 0); end;

13. Signed’s Synthesisable Operators comparson: =, /=,, >= arithmetic: sign -, sign +, abs, +, -, * concatenation: & Note that ** (exponent operator), “/”, mod, rem are unsynthesisable in general case.

14. Comparison Operators library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity max is port(a, b : in signed(7 downto 0); z : out signed(7 downto 0) ); end; architecture behavior of max is begin z b else b; end;

15. Boolean Operators: bitwire and library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity and_demo is port(a, b : in unsigned(7 downto 0); z : out unsigned(7 downto 0) ); end; architecture behavior of and_demo is begin z <= unsigned(std_logic_vector(a) and std_logic_vector(b)); end;

16. Boolean Operators: masking library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity max is port(a, b : in signed(7 downto 0); z : out signed(7 downto 0) ); end; architecture behavior of max is begin z <= a when signed(std_logic_vector(a) and “00001111”) /= “0” else b; end;

17. Boolean Operators: masking Clear the four least-significant bits by masking: z <= unsigned(std_logic_vector(a) and “11110000”); a=“01010101” ==> z =“01010000” set the four least-significant bits by masking and set the four most-significant bits: z <= unsigned(std_logic_vector(a) or “11110000”); a=“01010101” ==> z =“11110101”

18. Arithmetic Operators library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity negation_demo is port(a : in signed(7 downto 0); z : out signed(7 downto 0) ); end; architecture behavior of negation_demo is begin z <= -a; end;

19. Arithmetic Operators library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity negation_resize_demo is port(a : in signed(7 downto 0); z : out signed(8 downto 0) ); end; architecture behavior of negation_resize_demo is begin z <= -conv_signed(a,z’length); -- if a = -128?? end;

20. Arithmetic Operators: abs library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity abs_resize_demo is port(a : in signed(7 downto 0); z : out signed(8 downto 0) ); end; architecture behavior of abs_resize_demo is begin z <= abs conv_signed(a,z’length); -- if a = -128?? end;

21. Arithmetic Operators: + library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity add_resize_demo is port(a, b : in signed(7 downto 0); z : out signed(8 downto 0) ); end; architecture behavior of add_resize_demo is begin z <= conv_signed(a,z’length)+ conv_signed(b,z’length); -- no resize z<=a+b end;

22. Arithmetic Operators: * library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity multiply_demo is port(a, b : in signed(7 downto 0); z : out signed(7 downto 0) ); end; architecture behavior of multiply_demo is begin z <= conv_signed(a*b,z’length); -- a*b 16-bit result -- truncate to 8 bit end;

23. Shift functions: std_logic_arith signed and unsigned Shift left logical 4 bit shl is a function: shl(a,4) vs a sll 4:

24. Shift operators: built-in type Shift left arithemetic 4 bit (a sla 4):

25. Unsigned Shift right functions unsigned shift right logical 4 bit shr(a,4)

26. Singed Shift Right Functions signed shift right 4 bit ( shr(a,4) ==a sra 4):

27. Type Conversions 4 important numeric types: signed, unsigned, integer, std_logic_vector. It is generally good practice to choose appropriate types for your design. Conversion between types are sometimes necessary. Type conversion function: conv_type type:integer, signed, unsigned, std_logic_vector

28. Type Conversions Type conversion function: conv_type type:integer, signed, unsigned, std_logic_vector aSig:integer, signed, unsigned, std_logic_vector conv_integer(aSig): convert aSig to integer conv_integer(aInt, n): convert aInt to n-bit integer conv_unsigned(aSig,n): convert aSig to n-bit unsigned conv_signed(aSig,n): convert aSig to n-bit signed conv_std_logic_vector(aSig,n):convert aSig to n-bit std_logic_vector

29. Type Conversions library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity conversion_demo is port(value : in natural range 0 to 255; result : out unsigned(7 downto 0) ); end; architecture behavior of conversion_demo is begin result <= conv_signed(value,result’length); end;

30. Type Conversions std_logic_vector ==> signed or unsigned library iee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity conversion_demo is port(value : in std_logic_vector(7 downto 0); result : out unsigned(7 downto 0) ); end; architecture behavior of conversion_demo is begin result <= unsigned(value); end;

31. Constant values Constant values of signed and unsigned types can be represented by string value. Z <= “00000000”; -- msb on the left. Aggregate: Z 0); conv_type Z <= conv_unsigned(‘0’,8);

32. Mixing Types in Expressions type1 op type2 ==> what type? (op: +,-, …) signed > unsigned > integer signed > unsigned > std_ulogic see table 6.2, 6.3 and 6.4.