A Readout Electronics for MAPMT Matteo Turisini – E. Cisbani Italian National Institute of Health – INFN Rome 1 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

2 Outline ✤ Original Application ✤ Functional and Architectural Overview ✤ Front End and PCB details ✤ Pros and Cons (for RICH readout) ✤ RICH Optimization JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

Single Gamma Photon Imaging on Small Animal Different Detector Heads Electronics HV Power Supplies HeadSize(mm 2 )CollimatorScintillatorPMTMain Feature 150x50Pinhole Ø 1 mmLaBr 3 (Ce) 50x50x6 continuousH8500 HighQEBest Energy Resolution 250x50Pinhole Ø 1 mmCsI(Tl) 50x50 pitch 0.8 mmH9500Best Spatial Resolution 3100x100Pinhole Ø 1 mmNaI(Tl) 100x100 pitch 1.5 mm2x2 H8500Large Field of View + LOW VOLTAGE Small Animal Resolution ~1 mm S ingle P hoton E mission T omography 3 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

Requirements for SPET Self Triggering Trigger is internally generated Plug and Play Can be used by “non expert” Compactness Must sits in small room Analog readout Acquire charge for centroid estimation Scalability One to many detectors could be connected Flexibility Easily relocatable Acquisition Rate As large as possible (10 kevt/s at least) 4 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

5 Functional Overview 5 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

6 Architectural Overview BP FE CBPC PM + Adapter board PM PM Parallel Bus Event Builder FrontEnd Board (64 anodes) Control Board (4 BP) BackPlane (16 FE) high density cable USB 2.0 Light Detector Up to 64 FE boards = 4096 channels 1 FE = 1 Maroc chip JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

7 M ulti A node R ead O ut C hip From LHC - ATLAS 1)64 input channels 2)Single channel pream. gain selection 3)Multiplexed charge output (analog sample & hold) 4)Individual channel digital output (64 bit parallel) 5)Stable threshold for digital lines at 0.3 pe (~50fC) Technology: AMS Si-Ge 0.35 μm Chip Area: 16mm 2 Package : CQFP240 Consumption : 350 mW (5mW/ch) Voltage Supply :0-3.5 Volt JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

8 MAROC Single Channel Block Diagram FAST CHANNEL time information on interaction with the detector (10 ns) Configurable Threshold SLOW CHANNEL Charge measurement (30 to 210 ns) Analog or Digital output (MUX) Tunable shape MAROC Common:  Variable Preamp. Gain JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

✤ MAROC ✤ Local FPGA: ✤ MAROC Configuration ✤ First level trigger (SelfTrigger generation or external trigger) ✤ Analog data FIFO ✤ Digital pipeline ✤ Sparse readout ✤ External ADC ✤ Tunable Hold delay Front End Board 51mm x 68 mm 9 ASIC side FPGA side 9 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

 Passive Board with parallel bus (pBus)  Customizable, up to 16 front-end connectors  FE slots spacing fits Hamamatsu H8500 and 9500 mechanical constraints Back Plane 10 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

11 Control Board 103 mm x 173 mm  USB Controller  pBus Controller/ Driver  2 Input/Output Lines (include trigger/in and busy/out)  FPGA:  Interfaces (pBus, USB)  Second Level Trigger  Event Builder  Buffering (FIFO) JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

12 Electronics adapted to RICH prototypes tests Test Beam 2009 (LNF/BTF) Test Beam 2011 (CERN) more on the meeting JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

13 Pedestal stability 13 External Trigger (1÷10 5 Hz) RMS ~ 1 ADC channel Stable vs time JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

14 External Trigger Timing 14 Programmable / Hold Delay Line External Trigger propagation time from Control Board input to Front-End FPGA 55 ± 10 ns i × 1 ns i = 0,1,...,255. Trigger must arrive between 60 to 300 ns after the event (for analog readout) JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

15 Main Implemented Features Self- and External Trigger Event Rate = 5 kevts/sec (Analog Readout / Measured channel occupancy) Tunable threshold Short pipeline for binary data (never really used) Reconfigurable (FPGA) Power Consumption = 2.1 Watt (only 1 Front End) Single voltage supply = 3.5 Volt Dedicated software available (DAQ and Analysis) 15 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

16 Weakness for large apparatus Designed for compact (small) systems Use USB to connect to DAQ node (e.g. notebook)  USB transmission protocol somehow inefficient (75%)  USB cable < 5mt Currently not optimized for binary readout No reliable time information 16 JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

Features NOT needed in final RICH JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

Features needed in final RICH ✤ Electronics-Daq faster link (Optical/VME …) ✤ Binary pipeline (longer trigger latency and reduce dead time) ✤ Higher parallelism to read front end card (now cards are read sequentially) ✤ Improved pBus for large number of cards/channels ✤ Exclusive binary readout (faster acquisition, about factor of 10) ✤ Time information (?) [MAROC can provide time resolution at the level of 10 ns] JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

19 Conclusions ✤ Current system suitable for RICH prototyping ✤ Analog information very useful ✤ Firmware improvement possible (e.g. remove self triggering resources and extend buffering) ✤ Toward the final RICH ✤ Hardware and firmware modification needed ✤ Part of the MAROC resources will be not used (or used for calibration only) ✤ Binary line to be characterized for S.P.E. (e.g. minimum achievable threshold) JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

20 VME like Interrupt Handling JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

21 Data Transfer Protocol JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani

22 Event Builder Buffer 22 FIFO 8192 addresses 24 bit At present time charge data, overhead 3 % Once the system is well-characterized only digital information will be read out ×10 increment in event rate! Single Event 200 evt/sec Multi Event 5k evt/sec with ~ 400 complete channels JLab/CLAS12 RICH Meeting - 16/Nov/ Turisini/Cisbani