LCFI Collaboration Status Report LCUK Meeting Oxford, 29/1/2004 Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, QMUL, RAL

Joel Goldstein, RALLCUK 29/1/04 2 LCFI Research Programme R&D for a vertex detector at NLC or TESLA 1.Physics Studies Algorithm development and implementation Detector optimisation 2.Mechanical Development Ultra low-mass ladders FEA/physical models 3.Detector Development Fast CCD technology (50 MHz for TESLA) Custom CMOS readout chips

Joel Goldstein, RALLCUK 29/1/04 3 LC Vertex Detector 800 Mchannels of 20  20  m pixels in 5 layers Optimisation: –Inner radius (1.5 cm?) –Readout time (50  s?) –Ladder thickness (0.1% X 0 ?)

Joel Goldstein, RALLCUK 29/1/04 4 Physics Studies Preparing framework Many different options –Short term: SGV –Long term: JAS3 ZVTOP (SLD) Benchmarking starting 1.Implement flavour tagging algorithms in LC software 2.Quantify physics impact of different configurations

Joel Goldstein, RALLCUK 29/1/04 5 Mechanical Options Target of 0.1% X 0 per layer (100  m silicon equivalent) 1.Unsupported Silicon –Longitudinal tensioning provides stiffness –No lateral stability –Not believed to be promising 2.Semi-supported Ultra-thin Silicon –Detector thinned to epitaxial layer (20  m) –Silicon glued to low mass substrate for lateral stability –Beryllium has best specific stiffness –Composites, ceramics, foams... 3.Novel Structures

Joel Goldstein, RALLCUK 29/1/04 6 Mechanical Studies of Be-Si FEA SimulationsPhysical Prototyping Laser survey system Thinned CCD (  20 μm) Beryllium substrate (250 μm) Adhesive 0.2mm ~160 μm ripples at - 60°C Good qualitative agreement

Joel Goldstein, RALLCUK 29/1/04 7 New Approaches Be-Si unstable when cooled due to CTE mismatch Choose substrate with closer CTE match –100 μm carbon fibre –ceramic foam Micromechanical techniques.... Microstages replace glue pillars Sandwich UV lithography on dummy

Joel Goldstein, RALLCUK 29/1/04 8 Column Parallel CCD N+1 Column Parallel CCD Readout time = (N+1)/F out Separate amplifier and readout for each column

Joel Goldstein, RALLCUK 29/1/04 9 Prototype CP CCD CPC1 produced by E2V Two phase operation Metal strapping for clock 2 different gate shapes 3 different types of output 2 different implant levels  Clock with highest frequency at lowest voltage

Joel Goldstein, RALLCUK 29/1/04 10 CPC1 Results Noise ~ 100 electrons Minimum clock ~1.9 V Maximum frequency ~ 10 MHz –inherent clock asymmetry

Joel Goldstein, RALLCUK 29/1/04 11 CP Readout ASIC CPR1 designed by RAL ME Group IBM 0.25 μm process 250 parallel channels with 20μm pitch Designed for 50 MHz Data multiplexed out through 2 pads

Joel Goldstein, RALLCUK 29/1/04 12 CPR1 Testing Flash ADCs tested Voltage and charge amplifiers tested Voltage gain ~40 Very sensitive to timing and bias values Outstanding digital problems Voltage injection into ADC

Joel Goldstein, RALLCUK 29/1/04 13 Wirebonded Combination

Joel Goldstein, RALLCUK 29/1/04 14 Last Tuesday: Success! 4 channels with test signal 4 channels wirebonded to CCD Single channel histogrammed over 200 frames

Joel Goldstein, RALLCUK 29/1/04 15 Wirebonded Results Noise ~130 electrons Noise from preamps negligible Direct connections will be tested next

Joel Goldstein, RALLCUK 29/1/04 16 Future Plans Bump Bonding –Currently underway with VTT –Expect assemblies in March/April Test Programme –Radiation effects on fast CCDs (Liverpool/Lancaster) –High frequency clock propagation (Oxford) Next Generation ASIC –Cluster finding logic –Design work almost finished –Waiting for CPR1 results and final review Next Generation CCD –Design work starting in next few weeks –Detector scale device

Joel Goldstein, RALLCUK 29/1/04 17 Summary LCFI is on schedule and making good progress –Physics tools ready for detector optimisation –Semi-supported option studied in detail –New mechanical ideas discussed –CCD+ASIC operation achieved CP CCDs are viable technology for linear collider Next generation will be full-scale prototype CCDs Accelerator technology choice will determine path