1. 1 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory LCFI Detector R&D Status Report WP2 – Sensor Development WP3 – Readout and Drive Electronics WP4 – External Electronics WP5 – Integration and Testing  Introduction to the present Detector WP  Work during the last 6-month period  Current activities  Plans

2. 2 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Introduction to the Detector R&D Work Packages WP2 Sensor Development CPCCD and ISIS Design Simulations Interaction with the manufacturer WP3 Readout and Drive Electronics Design Simulations Support WP4 External Electronics Circuit Design PCB Design Simulations on clock propagation in CPCCD CPCCD transformer drive WP5 Integration and Testing Bump Bonding (VTT) Tests of CPCCD, readout chips and hybrid assemblies Firmware and software for tests Data analysis

3. 3 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory First CPCCD (CPC1) manufactured by e2V:  20 μm square pixels  750 (H)  400 (V) pixels CMOS readout chip (CPR1) designed at RAL Bump-bonded by VTT (Finland) CPC1 clocked to 25 MHz stand-alone, metal- strapped gates for efficient clock propagation CPC1 optimised for low clock amplitude and low drive power – works with 1.9 V pp clocks Readout chip has amplifiers, 5-bit ADCs and FIFO per column Main detector R&D at LCFI: Hybrid assembly with Column-Parallel CCD (CPCCD) and CMOS ASIC Bump-bonded CPC1/CPR1 in a test PCB CPCCD Work

4. 4 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory 5.9 keV X-ray hits, 1 MHz column-parallel readout Voltage outputs, non- inverting (negative signals) Noise  60 e- Charge outputs, inverting (positive signals) Noise  100 e- First time e2V CCDs have been bump-bonded High quality bumps, but assembly yield only 30% - reason still unclear Differential non-linearity in ADCs (100 mV full scale) – addressed in CPR2 Bump bonds on CPC1 under microscope CPCCD Work

5. 5 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Yield summary from batch 1 AssemblyLeft hand side chipRight hand side chipCCD 1OK 2 Problem 3OK Problem 4OKLow resistance CGND-VDDProblem 5OK 6 Short CGND-VDDOK 7Subtle defect (VPRE-VDC)Short CGND-VDDOK CPCCD Work – Hybrid Assembly Testing (WP5) Summary: ● Only 4 complete assemblies fully working, out of 13 (30% yield) ● Right hand side chips show problems: ● Short between the power supplies or defective in other ways ● Parasitic connection to SS ● Readout chips diced by IBM exhibit yield close to 100% ● All CCDs have been DC probed at e2V – 23 good chips (out of 24). ● Dicing has been checked, does not seem to be the problem ● What is the explanation?

6. 6 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Possible problem explanation (1) CGND pad, parasitic connection to SS? Mechanical damage? SS Right hand side of the CPCCD CPCCD Work – Hybrid Assembly Testing (WP5)

7. 7 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Possible problem explanation (2) CGND pad, parasitic connection to SS? Mechanical damage? CGND SS Right hand side of the CPCCD CPCCD Work – Hybrid Assembly Testing (WP5)

8. 8 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Right-hand side CPR1, 100 mA between CGND and SS (360 Ω between them) Thermal images Batch 1, Assembly 2, right hand side chip CPCCD Work – Hybrid Assembly Testing (WP5)

9. 9 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory CPC2 Design Three different chip sizes with common design:  CPC2-70 : 92 mm  15 mm image area  CPC2-40 : 53 mm long  CPC2-10 : 13 mm long Compatible with CPR1 and CPR2 Two charge transport sections Choice of epitaxial layers for different depletion depth: 100 .cm (25 μm thick) and 1 k .cm (50 μm thick) Baseline design allows few MHz operation for the largest size CPC2

10. 10 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory CPC1 did not have optimal drive conditions due to single level metal Novel idea from LCFI for high-speed clock propagation: “busline-free” CCD:  The whole image area serves as a distributed busline  50 MHz achievable with suitable driver in CPC2-10 and CPC2-40 (L1 device)  Transformer drive for CPC2, will evolve into dedicated driver chip Φ1 Φ2 Level 1 metal Polyimide Level 2 metal Φ2 Φ1 To multiple wire bonds To multiple wire bonds 1 mm CPC2 Clock Driving

11. 11 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory CPC2 + ISIS1 Wafer 2 ISIS chips CPC2-70 CPC2-40 CPC2-10

12. 12 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory CPC2 + ISIS1 Manufacture ● Delivery was scheduled to March 2005 ● Delays at e2V due to equipment breakdown ● Operator error caused the entire batch to be scrapped ● e2V immediately started new batch at their expense ● First devices expected mid July ● “Bad batch” processed to 1 st polysilicon, could be used for thinning studies ● New diamond grinder at e2V comes next month

13. 13 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Beam-related RF pickup is a concern for all sensors converting charge into voltage during the bunch train; The In-situ Storage Image Sensor (ISIS) eliminates this source of EMI:  Charge collected under a photogate;  Charge is transferred to 20-pixel storage CCD in situ, 20 times during the 1 ms-long train;  Conversion to voltage and readout in the 200 ms-long quiet period after the train, RF pickup is avoided;  1 MHz column-parallel readout is sufficient; In-situ Storage Image Sensor (ISIS)

14. 14 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Additional ISIS advantages:  ~100 times more radiation hard than CCDs – less charge transfers  Easier to drive because of the low clock frequency ISIS combines CCDs, active pixel transistors and edge electronics in one device: specialised process Development and design of ISIS is more ambitious goal than CPCCD Plus additional logic for row selection and clock gating (not shown) In-situ Storage Image Sensor (ISIS)

15. 15 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory ISIS1 “Proof of principle” device (ISIS1) designed by e2V: 16  16 array of ISIS cells with 5-pixel buried channel CCD storage register each; Cell pitch 40 μm  160 μm, no edge logic (CCD process) Size  6.5 mm  6.5 mm ● Test board designed by a Sandwich student at RAL ● ISIS1 fits into 100-pin socket ● Software being written

16. 16 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Simulations on CMOS-based ISIS ● Targeting 0.25 μm or 0.18 μm process ● 3.3 V maximum voltage ● 6.5 nm SiO 2 as both CCD and transistor gate dielectric ● Non-overlapping polySi gates (0.35 μm gap, 0.25 μm design rules ) Keeping in touch with: ● Jim Janesick (Sarnoff) – simulations, advice, possibly MPW ● Chronicle Technology – design ● e2V: David Burt, Ray Bell – CCD experts ● “Fine Pixel ISIS” – new concept from e2V Simulations for the next generation CMOS-based ISIS2 ● Thin oxide unfavourable for the CCD structure – dual gate oxide possible ● LCFI solution – modify the buried channel implant, keep one oxide only ● Major simplification, reduce costs

17. 17 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory DIOS simulated doping (part of ISE-TCAD) ● P+ shield implant: 800 keV (B), 5  10 11 cm -2 ● Buried channel: 200 keV (P), 4  10 11 cm -2 and 40 keV (P), 3  10 11 cm -2 ● Annealed at 1050  C for 40 min Analytical and simulated doping profiles Analytical profiles: Gaussians

18. Alternative ISIS structure Proposed super-pixel 20 µm 4µm, 4Ø line Apertures in p-well Charge can be collected when a high phase is over a p-well aperture Commercial in confidence Pure CCD process, simpler than the ISIS but Too many transfers? Radiation damage concerns Complicated output structure

19. 19 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory CPR2 designed for CPC2 Results from CPR1 taken into account Designed by the Microelectronics Group at RAL Size : 6 mm  9.5 mm 0.25 μm CMOS process (IBM) Manufactured and delivered February 2005 Bump bond pads Wire/Bump bond pads CPR1 CPR2 Voltage and charge amplifiers 125 channels each Analogue test I/O Digital test I/O 5-bit flash ADCs on 20 μm pitch Cluster finding logic (2  2 kernel) Sparse readout circuitry FIFO WP3 : CPCCD Readout Chip CPR2

20. 20 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory WP3 : CPR2 ● Improved clock distribution, should improve ADC performance ● Sparse readout circuitry with position and timestamp, outputs 4  9 pixels/cluster ● Charge amplifiers:  Half with 3 fF feedback capacitor (as in CPR1)  Half with 2 fF capacitor for increased gain ● Voltage amplifiers:  Selectable 10 ns low-pass filter (was 5 ns in CPR1) ● Direct analogue outputs from one voltage and charge amplifier ● Three analogue inputs to one voltage channel triplet ● Test register with 3 functions:  Input to sparsifying logic  ADC data capture  Selection of an ADC channel for direct output

21. 21 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory WP3 : Testing CPR2 ● Test board made at Oxford U ● Work in the CCD lab has begun ● First results indicate the chip is operational ● Testing at RAL/ID imminent ● 2 wafers for bump-bonding available

22. 22 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory WP4 : Transformer drive for CPC2 Tests of planar transformers with dummy capacitive load Requirements: 2 Vpp at 50 MHz over 40 nF (half CPC2-40) Frequency scan with network analyser, performance promising Parasitic inductance of bond wires is a major effect – fully simulated Different planar transformers on 10- layer PCB Size : 1 cm Air core operation from  1 MHz to > 70 MHz unloaded Prototypes ready to be incorporated into the CPC2 test board (under design now at Oxford U) IC driver could be a better solution Design of CPCCD driver chip - CPD1 in WP3

23. 23 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory WP4 : External electronics Base VME module (BVM2): ● Large FPGA on-board ● 32 TTL I/O ● 32 LVDS I/O ● Two 1M  16-bit SRAM ● Two external clocks ● Daughterboard for extensions: delay lines, clock management, etc. ● Workhorse for the next 3 years ● Two modules manufactured (ver. 1) ● Second version being designed

24. 24 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Immediate Plans WP2: ● Get CPC2 and ISIS1 ● Continue ISIS simulations, WP3: ● Provide support for CPR2 tests ● Start the design of CPD1 WP4: ● Design motherboards for CPC2+CPR2 (bump-bonded and stand-alone) ● Transformer drive, work on the driver chip WP5: ● Test CPR2, CPC2, ISIS1 ● Bump-bond CPC2 to CPR2 and test

25. 25 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Readout Chip Dicing – Upper Left Corner IBM dicing VTT batch 1 VTT batch 2 CPCCD Work – Hybrid Assembly Testing (WP5)

26. 26 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory How CPC1+CPR1 work ADCBLR+ ADC _ OG RG RD OD +12.7 V +18.0 V OG RD +17.0 V 2.5 V CPR-1CPC-1 110 µA BC SC BC Gain ≈ 40 ≈ +14.0 V +15.2 V +2.0 V FB_V FB_Q VDC Floating CPR-1 ground LPF 3 fF X-ray signal ≈ 200 mV X-ray signal ≈ 90 mV Correlated Double Sampling

27. 27 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory p+ shielding implant n+ buried channel (n) substrate (p+) storage pixel #1 storage pixel #20 sense node (n+) Charge collection row select reset gate Source follower V DD p+ well reflected charge photogate transfer gate Reset transistor Row select transistor output gate High resistivity epitaxial layer (p) To column load n+ buried channel (n) substrate (p+) storage pixel #1 storage pixel #20 sense node (n+) Charge collection row select reset gate V DD p+ well reflected charge photogate transfer gate output gate High resistivity epitaxial layer (p) Design A Design B

28. 28 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory 1 Storage gate 2 4 5 6 20 19 18 17 7 8 RSEL OD RD RG OS to column load Storage gate 3 Transfer gate 8 Output gate Output node Photogate Charge generation Transfer Storage Readback from gate 6 Idea by D. Burt and R. Bell (e2V)

29. 29 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory 05 05 0000 0000 0000 0000 0000 0000 0000 0550 0000 0000000 0000000 0000000 0000000 0000000 00000 00000 Cluster found Expanded cluster to be read out 0000000 0000000 000 000 000 000 000 000 000 000 000 Cluster Finding in CPR2

30. 30 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory Yield summary from batch 1 AssemblyLeft hand side chipRight hand side chipCCD 1OK 2 Problem 3OK Problem 4OKLow resistance CGND-VDDProblem 5OK 6 Short CGND-VDDOK 7Subtle defect (VPRE-VDC)Short CGND-VDDOK Problem description: ● Parasitic ohmic connection between right hand side chip substrate (CGND) and CCD substrate (SS) ● Should see reverse-biased diode between CGND and SS ● The problem disappears when right hand side chip is removed ● Not caused by contamination, resistance too small (e.g. 360 Ω) CPCCD Work – Hybrid Assembly Testing (WP5)