07 October 2004 Hayet KEBBATI -1- Data Flow Reduction and Signal Sparsification in MAPS Hayet KEBBATI (GSI/IReS)

07 October 2004 Hayet KEBBATI -2- Pixel Sensors applied to vertex detector  Hybrid Pixel Detectors  Fast readout and radiation hardness device,  Sizeable pixel pitch due to readout circuitry surface,  High material budget.  Charge Coupled Devices -CCD-  High density due to reduced pitch size,  Poor radiation hardness and long readout time.  Benefits from constant decrease of technology size  higher pitch density,  Can be thinned down to the thickness wanted => less material budget compared to hybrid devices,  Fast readout and radiation tolerant compared to CCD,  But radiation hardness always far behind hybrid devices,  Cost-effective and easily available CMOS Process.  Monolitic Active Pixel Sensors -MAPS-

07 October 2004 Hayet KEBBATI -3- System on a Chip (SoC) Signal Processing Part Sensor Digital Part Analog part Interface Part (ADC)  At the first Silicon tracking Station (5cm), particle densities have values up to 2 hits/mm².event,  Fast readout (100ns/event)  Huge data flow 1.6 Tera bits/sec (output size=1 bit),  Hit Extraction and data sparsification  Data flow of 8 Giga bits/sec  Implementation of on-chip processing forming a System on Chip  Parallel readout  40 transmission lines per reticle (20mmx20mm), Freq=200 MHz (output size=1 bits) CMOS Sensor -MAPS- : Data Flow Reduction

07 October 2004 Hayet KEBBATI -4- Control and address Electronics Fast signal processing and data sparsification  Signal digitalisation Storage threshold values needed during data sparsification Surface ratio (B 2 /B 1 ) must be as small as possible Matrix of Pixel Control ELN Sparcifi cation Memori- sation Smart Detector Reticle Band Height of non- sensitive part B2B2 Sensitive part Control and processing part ADC Band Height of sensitive part B1B1

07 October 2004 Hayet KEBBATI -5- Charge Sensitive Element : CDS with clamping capacitor architecture o nwell/p-epi diode biased by a bias forward diode to convert particle charge to voltage, o Noise sources : shot noise, FPN, flicker noise and thermal => CDS technique o On pixel CDS and amplification => good signal to noise ratio and T readout =100ns. VA Vclamp vdd gnd SF sample read clamp Cac Cclamp Csample Vx 2 diodes’s Self reverse bias charge sensitive element SF Vout

07 October 2004 Hayet KEBBATI -6- Signal Sparsification Method Hit 2 3 Steps : 1) Scanning clusters of 3x3 pixels 2) Compare pixels and clusters with seed threshold and cluster threshold value 3) Extract valid clusters seed_thre=7 mv cluster_thre=20 mv

07 October 2004 Hayet KEBBATI -7- Hit output = W pix. 5 + W adr (cluster 5) W pix R occ Flow Reduction RatioData Flow/Reticle 3 bits4%67%200 Giga bits/sec 8%33% 10%17% 4 bits4%70%240 Giga bits/sec 8%40% 10%25% Hit output = W pix. 2 + W adr (heavy center, processing part surface>>) W pix R occ Flow Reduction RatioData Flow/Reticle 3 bits4%79%128 Giga bits/sec 8%57% 10%47% 4 bits4%82%144 Giga bits/sec 8%64% 10%55% Data Flow with On-chip Processing R occ is the hit occupancy rate = number of hits / total number of pixels W adr is the binary length of the address of the pixel position W pix is the binary length of the signal corresponding to the pixel voltage

07 October 2004 Hayet KEBBATI rows 1000 columns bits ADC Seed pixel and cluster Comparisons Cluster Extraction Threshold values Memorisation Sub-bloc Detector Structure Pitch = 20 µm  Pixel Readout time = 100ns => Readout time = 10 µs => occupancy rate up to 8% at station 1 closest to the beam  Column parallel readout,  Digitalization of the output data of each column (3 bits ADC). (2 mm) (20 mm) Sensitive part Control and processing part

07 October 2004 Hayet KEBBATI OR Gates Tree FSM FIFO 8 ADC counter OR Gates Tree FSM FIFO 8 ADC 200 MHz 50 MHz 10 MHz  Surface = 20mm 2  Processing surface to sensitive surface ratio=1/2 Data Sparsification Implementation results (0.35 µm)

07 October 2004 Hayet KEBBATI -10- row decoder column decoder column mux, write buffers, sense amplifiers, DRAM cell write bit line gnd read bit line 3 T DRAM 3.5 x 5.5  m = 2.5 x 3.92 SDRAM Memory Strucure adr write data pre read adr data valid data Write Cycle Read Cycle

07 October 2004 Hayet KEBBATI -11- Memory of 512x26 bits in 0.25µm technology Regular layout with silicon surface saving Test data maintain time in DRAM cells Test of circuit behavior under radiation : number and type of errors  detection and correction bits Surface : 320µmx930µm Access delay : 2.5 ns Power dissipation: 7 mW SDRAM Implementation Results

07 October 2004 Hayet KEBBATI -12- Summary  Real-time data processing  Readout time = 10µs => hit occupancy rate up to 8% in worst case  Processing surface to sensitive surface ratio = ½  To improve the ratio : 1.Increase the pitch  hit occupancy rate rise 2.Parallel readout by 2 rows  High power dissipation  SDRAM design in 0.25 µm technology  Surface = 320µmx930µm  Access time = 2.5 ns Options to reduce hit occupancy:  Optimize STS geometry to avoid hot spots ? Use hybrid pixels in the hottest area