Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010

Outline Introduction Problem Formulation Constraints and Terminologies Algorithm Experimental Results Conclusions

Introduction To ease the efforts of bus routing in later routing stage, it is desirable to consider it in the early floorplanning stage. Bus-driven floorplanning targets on obtaining a bus- routable floorplan such that the chip area and the bus area are minimized.

Introduction Without taking the position and orientation of the bus pin into consideration, it may have following impacts on bus routing:  Bus twisting: it makes the signal wires cross at a point and transmit the wrong data.  Via increasing: several vias occur on the bend of a bus that have adverse effects on the bus delay.  Delay variation: different driver-load wirelength between bus bits causes delay variation among all bits of the bus.

Introduction

Problem Formulation Bus-pin aware bus-driven floorplanning problem: Input:  A set of n modules M={m 1, m 2, …, m n }, each module m i is associated with height h i and width w i.  A set of m buses B={b 1, b 2, …, b m }, each bus b j has a width t j and goes through a set of modules. Objective:  Decide the position and orientation of the bus pins on each module.  Determine the routing path of each bus such that no overlapping occurs.  Minimize the chip area and the total bus area.

Constraints and Terminologies Capacity constraint  bw 2 + bw 3 > max(w 1,h 1 ), the capacity of m 1 is not enough for both B 2 and B 3 to pass through.

Constraints and Terminologies Definition: A bus pin of an n-bit bus consists of n pins. A bus pin is oriented horizontally or vertically. The position of the bus pin can be placed on any of the four boundaries of the module. The orientation of the bus pin is defined as the direction from the LSB to MSB.

Constraints and Terminologies Bus pin flipping is used to change the orientation of the bus pins.

Constraints and Terminologies Wirelength deviation represents the wirelength difference among all bits of the bus. The MSB-LSB wirelength deviation:  dev = |len(MSB)-len(LSB)| A turning node can contribute –D, 0 or +D to the MSB-LSB wirelength difference  D = 2BW

Algorithm Derive a floorplan by using the sequence pair representation. Modified Prim’s algorithm is used to obtain bus routing topologies. Perform wirelength reduction algorithm for each bus to reduce the wirelength. Assign each bus to different layers. Orientation determination and deviation minimization

Algorithm In each SA iteration, three operations to perturb:  Rotate  Reverse  Swap Cost = αA + βB + γI  A is the chip area  B is the bus area  I is the number of invalid bus nets

Modified Prim’s Algorithm Construct the MST for bus modules. Check the capacity of each module to avoid violating capacity constraint. If some edges violate the constraint, then other edge will be selected to connect the MST.

Bus Ordering and Coordinate Determination Sequence pair is (1234, 2314) m 1 is placed above m 2, B 2 passing through m 1 has to be placed above B 1 passing through m 2. OCG contains a cycle means the two bus conflict with each other and one of them is regarded as infeasible.

Bus Ordering and Coordinate Determination The coordinate of each horizontal bus B i is: y max = max{y i | i = 1, 2, …, k} k is the number of the modules passed by the bus. y i is the y coordinate of each module.

Wirelength Reduction

Layer Assignment Two layers for bus routing. Layer assignment becomes 2-coloring problem. Construct a conflict graph. Choose the node that has the max degree to assign it to layer 1, and all its neighbors are assigned to layer 2. If odd cycle occurs in the conflict graph, one of the buses are regarded as infeasible.

Orientation Determination and Deviation Minimization There are 150 possible bus shapes including the bus pin position between any two modules. Conclude 24 patterns for all possible bus shapes.

Orientation Determination and Deviation Minimization Choose the pattern holding the best accumulated deviation at the module.

Orientation Determination and Deviation Minimization

Experimental Results

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Conclusions This paper proposed a high-quality bus-driven floorplanning algorithm considering the practical impacts of the bus pins.