1. 1 Modern Floorplanning Based on Fast Simulated Annealing Tung-Chieh Chen* and Yao-Wen Chang* # Graduate Institute of Electronics Engineering* Department of Electrical Engineering # National Taiwan University, Taipei, Taiwan April 5, 2005

2. National Taiwan University 2 Outline ․ Introduction ․ Fast simulated annealing scheme ․ Fixed-outline floorplanning ․ Bus-driven floorplanning ․ Conclusion

3. National Taiwan University 3 Outline ․ Introduction ․ Fast simulated annealing scheme ․ Fixed-outline floorplanning ․ Bus-driven floorplanning ․ Conclusion

4. National Taiwan University 4 Introduction ․ Popular modern floorplanning constraints Fixed-die (fixed-outline) constraint Block positions and interconnect constraints ․ Two types of modern floorplanning problems Fixed-outline floorplanning (FOF) Bus-driven floorplanning (BDF) Need to consider the interconnect and block positions simultaneously. ․ Our floorplanner is based on the B*-tree floorplan representation and a fast three-stage simulated annealing scheme, called Fast-SA.

5. National Taiwan University 5 Previous Work ․ Fixed-outline floorplanning (FOF) Adya et al. (ICCD 2001) -- Parquet Present new moves to guide local search. Lin et al. (ASPDAC 2004) -- GFA Use evolutionary search. However, both success rates are not high enough when whitespace is small. ․ Bus-driven floorplanning (BDF) Rafiq et al. (ISPD 2002, ISCAS 2002) The bus is composed of wires connecting only two blocks. Not general for real bus designs. Xiang et al. (ICCAD 2004) General BDF allows a bus to connect multiple blocks. Use the sequences pair (SP) representation.

6. National Taiwan University 6 Our Contribution ․ Propose a fast three-stage simulated annealing scheme (Fast-SA). ․ For the fixed-outline floorplanning (FOF) Propose a new objective function and an adaptive Fast-SA. Obtain much higher success rates. ․ For the bus-driven floorplanning (BDF) Explore the feasibility conditions of the B*-tree with the bus constraints. Reduce 20% (50%) dead space on average for the floorplanning with hard (soft) blocks, compared with the most recent work by Xiang et al.

7. National Taiwan University 7 B*-Tree Floorplan Representation ․ Chang et al., “B*-tree: A new representation for non- slicing floorplans,” DAC-2k. Given a B*-tree, the legal floorplan can be obtained in amortized linear time. Left child: the lowest, adjacent block on the right (x j = x i + w i ). Right child: the first block above, with the same x-coordinate (x j = x i ). n0n0 n7n7 n8n8 n9n9 n1n1 n2n2 n3n3 n4n4 n5n5 n6n6 A compacted floorplan The corresponding B*-tree b0b0 b7b7 b8b8 b9b9 b1b1 b2b2 b3b3 b6b6 b5b5 b4b4 (x 0, y 0 ) x 1 = x 0 w0w0 x 7 = x 0 + w 0

8. National Taiwan University 8 Outline ․ Introduction ․ Fast simulated annealing scheme ․ Fixed-outline floorplanning ․ Bus-driven floorplanning ․ Conclusion

9. National Taiwan University 9 Simulated Annealing (SA) Using B*-trees ․ Non-zero probability for up-hill climbing: p = min{1, e -ΔC/T } ․ Perturbations (neighboring solutions) Op1: Rotate a block. Op2: Move a node/block to another place. Op3: Swap two nodes/blocks. Op4: Resize a soft block. ․ The cost function is based on problem requirements. (fixed-outline constraint, bus constraint, etc.)

10. National Taiwan University 10 Simulated Annealing Schedule ․ Classical annealing schedule Classical temperature updating function, λ is set to a fixed value (0.85 as recommended by most previous work) T new = λT old, 0 < λ< 1 ․ TimberWolf annealing schedule (Sechen and Sangiovanni-Vincentelli, DAC-86) Increase λ gradually from its lowest value (0.8) to its highest value (approximately 0.95) and then gradually decreases λ back to its lowest value.

11. National Taiwan University 11 Fast Simulated Annealing (1/2) ․ Reduce the number of “up-hill” moves in the beginning ․ Consists of three stages The high-temperature random search stage The pseudo-greedy local search stage The hill-climbing search stage ․ Comparisons for the temperature vs. search time: Time Temperature Classical SA TimberWolf SA Fast-SA Time III III Time (a) (b) (c) S Cost State (Solution space) local optima global optimum Probability for up-hill climbing: p = min{1, e -ΔC/T }

12. National Taiwan University 12 Fast Simulated Annealing (2/2) ․ Temperature update ․ If is large, the temperature decreases slowly. ․ If is small, the temperature decreases quickly. The temperature for n th iteration Average uphill cost Initial acceptance rate Average cost change since the SA started User-specified constants P k,c

13. National Taiwan University 13 Convergence and Stability for Fast-SA ․ Classical SA TimberWolf SA Fast-SA, k=1 (no greedy local search) Fast-SA, k=7 ․ Ran the circuit n100 for 10 times. ․ Fast-SA has better convergence speed than TimberWolf SA and classical SA. Classical SATimberWolf SA Fast SA (no greedy local search) Fast SA

14. National Taiwan University 14 Outline ․ Introduction ․ Fast simulated annealing scheme ․ Fixed-outline floorplanning ․ Bus-driven floorplanning ․ Conclusion

15. National Taiwan University 15 Fixed-Outline Constraints ․ Two user-specified parameters: Γ: maximum white-space fraction, and R*: desired aspect ratio (height/width) ․ The outline (height H* and width W*) is defined by: ․ Use the same formulation as Adya et al. (ICCD-2001). Γ =0.15 H* W* R*=2 H* W* R*=1 Γ =0.50

16. National Taiwan University 16 Cost Function for Fixed-Outline Floorplanning ․ Cost for a floorplan F A Chip area Area weight W Wirelength Wirelength weight R* Desired aspect ratio R Current floorplan aspect ratio Chip area WirelengthAspect ratio penalty

17. National Taiwan University 17 Adaptive Simulated Annealing ․ Best aspect ratio of the floorplan in the fixed outline is not the same as that of the outline. ․ Shall decrease the weight of aspect ratio penalty to concentrate on the floorplan wirelenth/area optimization. An adaptive method to control the weights in the cost function is used according to n most recent floorplans found. The more feasible floorplans, the less aspect ratio penalty. (a) (b) Decrease aspect ratio penalty

18. National Taiwan University 18 Exp: Fixed-Outline Floorplanning (1/2) ․ Success rate vs. aspect ratio on circuit n100 n100, Γ=10% Parquet-2: SP (TVLSI-2003) GFA: NPE (ASPDAC-2004) Ours: B*-tree Avg. success rate16.6%30.3%99.7% Avg. dead space7.32%6.26%5.79% Avg. dead space ratio1.261.081.00 Avg. runtime (sec)40.244.527.6 Avg. runtime ratio1.461.611.00 Γ =15% Γ =10% ․ On a Pentium 4 1.6GHz PC

19. National Taiwan University 19 Exp: Fixed-Outline Floorplanning (2/2) ․ Wirelength optimization under the fixed-outline constraint. ․ Obtain 20% less wirelength on average, reduce 55% runtime on average, compared to Parquet. Circuit Aspect Ratio R * Parquet-2.1: SPOurs: B*-tree Wire (mm)Time (sec)Wire (mm)Time (sec) ami33 164.62346.316 265.92448.911 380.92367.715 472.72461.414 Average71.02456.114 ami49 17532575217 27922573918 39642585818 49892578720 Average8752578418 Comparison1.201.551.00 ․ On a Pentium 4 1.6GHz PC

20. National Taiwan University 20 Fixed-Outline Floorplanning Results Circuit: n100 Circuit: ami49

21. National Taiwan University 21 Outline ․ Introduction ․ Fast simulated annealing scheme ․ Fixed-outline floorplanning ․ Bus-driven floorplanning (BDF) ․ Conclusion

22. National Taiwan University 22 BDF Problem Formulation ․ Given n rectangular macro blocks B = { b i | i = 1, …, n } and m buses U = { u i | i = 1, …, m }, each bus u i has a width t i and goes through a set of blocks B i. Decide the positions of macro blocks and buses, and bus u i goes through all of its blocks. Minimize the chip/bus area. No overlap between any two blocks or between any two horizontal (vertical) buses. A feasible horizontal bus u =. y max = y c + h c y min = y b y max - y min ≥ t

23. National Taiwan University 23 B*-trees Properties for Bus Constraints (1/4) ․ Left child The lowest, adjacent block on the right ( x j = x i + w i ) Property 1: In a B*-tree, the nodes in a left-skewed sub- tree may satisfy a horizontal bus constraint. b0b0 b7b7 b8b8 b9b9 b1b1 b2b2 b3b3 b6b6 b5b5 b4b4 n0n0 n7n7 n8n8 n9n9 n1n1 n2n2 n3n3 n4n4 n5n5 n6n6

24. National Taiwan University 24 B*-trees Properties for Bus Constraints (2/4) Property 2: Inserting dummy blocks of appropriate heights, we can guarantee a horizontal bus with blocks whose corresponding B*-tree nodes are in a left- skewed sub-tree

25. National Taiwan University 25 B*-trees Properties for Bus Constraints (3/4) ․ The height of the dummy block D i : ․ An example of inserting dummy blocks to satisfy a horizontal bus.

26. National Taiwan University 26 B*-trees Properties for Bus Constraints (4/4) ․ Right child The first block above, with the same x-coordinate ( x j = x i ). Property 3: In a B*-tree, the nodes in a right-skewed sub-tree can guarantee the feasibility of a vertical bus.

27. National Taiwan University 27 Infeasible Twisted-Bus Structure ․ Consider two buses simultaneously, we cannot always fix the horizontal bus constraint by inserting dummy blocks. ․ Should discard such a tree configuration. u 1 = {b 0, b 3 } u 2 = {b 2, b 6 }

28. National Taiwan University 28 Bus-Overlapping ․ Use dummy blocks to avoid bus-overlapping while considering multiple buses. u 1 = {b 0, b 4 } u 2 = {b 2, b 3 } u 1 = {b 0, b 4 } u 2 = {b 2, b 3 }

29. National Taiwan University 29 Our BDF Algorithm (1/2) ․ Use simulated annealing to search for a desired solution. Cost of a floorplan F, buses U: A chip area B bus area M number of unassigned buses

30. National Taiwan University 30 Our BDF Algorithm (2/2) Initialize floorplan Perturb and pack “Twisted-bus structure” exists? Report the best floorplan Compute floorplan cost (quality) Simulated annealing iterations Adjust heights of dummy blocks Pack and decide bus location yes no Cooling down

31. National Taiwan University 31 Soft Macro Block Adjustment ․ Key: Line up with adjacent blocks Each soft block has four candidates for the block dimensions. ․ Advantage: fast and reasonably effective ․ Similar idea by Chi et al., Chung Yuan Journal, 2003. b2b2 b1b1 b2b2 b0b0 b4b4 b3b3 b5b5 L 3 R 3 T3B3T3B3 b0b0 b1b1 b4b4 b3b3 b5b5 (a) (b) xx yy R3R3

32. National Taiwan University 32 Exp: Bus-Driven Floorplanning Block typeHard Macro BlocksSoft Macro Blocks Circuits Block # Bus # SP: Xiang et al. (ICCAD 2003) B*-tree: Ours SP: Xiang et al. (ICCAD 2003) B*-tree: Ours Time (sec) Dead space Time (sec) Dead space Time (sec) Dead space Time (sec) Dead space apte95114.11%81.59%120.72%30.02% xerox106123.88%53.85%130.95%60.10% hp1114285.02%204.47%280.62%110.03% ami33-1338616.02%195.69%620.94%350.33% ami33-23318816.10%223.87%861.27%350.73% ami49-1499985.42%285.34%1010.85%650.51% ami49-249122786.09%435.45%2810.84%900.67% ami49-349152657.40%664.74%2681.09%1090.92% Average1045.51%264.38%1060.91%470.41% *SP: Hua Xiang, Xiaoping Tang, and Martin D.F. Wong, “Bus-driven floorplanning”, ICCAD 2003. The platform of SP is Intel Xeon 2.4GHz. ․ MCNC benchmark on Pentium 4 2.8GHz. Obtain 20% (55%) less dead space on average for hard (soft) macro blocks.

33. National Taiwan University 33 BDF Result ․ MCNC ami49-3 with soft block adjustment. ․ It has 49 macro blocks and 15 buses.

34. National Taiwan University 34 Outline ․ Introduction ․ Fast simulated annealing scheme ․ Fixed-outline floorplanning ․ Bus-driven floorplanning ․ Conclusion

35. National Taiwan University 35 Conclusion ․ Have proposed algorithms for the modern floorplanning problems with fixed-outline constraints and bus-constraints based on the new Fast-SA scheme. ․ Have shown Fast-SA leads to faster and stabler convergence to desired floorplan solutions. ․ Have shown the efficiency and effectiveness of our floorplanning algorithms for fixed- outline/bus-driven floorplanning.

36. National Taiwan University 36 Thank you for your attention! B*-tree 2005 will be available soon at http://eda.ee.ntu.edu.tw/research.htm http://eda.ee.ntu.edu.tw/research.htm B*-tree 1.0 (year 2000) + new perturbations + Fast-SA