The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – Lab 7 MOSFET Parameters.

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The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – Lab 7 MOSFET Parameters and Scaling Effects Ritu Bajpai October 24, 2008

CMOS Scaling Devices are constantly shrinking in an effort to increase the number of devices on a chip. The state-of-the-art mass production is moving into ~45nm. Clock speeds are scaled up to increase performance.

Effects on the device Short-channel effects on V T : If we reduce the channel length beyond a certain limit the source and drain depletion regions begin to affect the threshold voltage. Velocity saturation: With devices getting smaller they are exposed to high electric fields leading to drift velocity reaching its upper bound.

Effects on the device Gate leakage current (IG):The gate dielectric is needed to prevent charge from passing from the gate to channel of a MOSFET. All insulators, when sufficiently thin, allow some electrons, and thus some current, to pass through due to quantum mechanical effects.

Effects on the device Sub threshold current (ID): This is the current flowing through the transistor when it is nominally off (I off ). Ideally we want this current to be low. But like I on it is also proportional to (V GS -V T ).

Effects on the circuit Decreased supply voltage: As supply voltage is reduced, the charge stored will be small. With larger subthreshold leakage current, coupling noise etc is will be a challenge to get circuits to operate properly. Increased role of wiring resistance, inductance and capacitance.

Effects on the circuit Interconnect coupling: Wires are getting thinner but not decreasing as rapidly in height. This makes them look like tall thin conductors which form parallel plate capacitors. IR Drop: Narrow wires have a non negligible resistance. Electromigration: This involves migration of metal molecules due to high current densities and narrow line widths leading to a short or open in the metal line.

Spice MODELS The standard spice model is not sufficient to capture all of these effects. There have been many upgrades to it in order to increase it’s effectiveness. Level 1~5 Parameters Level 49~100 Parameters

Review of Spice Parameters.model nmos nmos Level=1 + Vto=1.0Kp=3.0E-5Gamma= Phi=0.65Lambda=0.02Tox=0.1u + Nsub=1.0E+15Nss=1.0E+10Ld=0.01u + Tpg=1.00Uo=700.0Af=1.2 + Kf=1.0E-26Is=1.0E-15Js=1.0E-8 + Pb=0.75Cj=2.0E-4Mj=0.5 + Cjsw=1.00E-9Mjsw=0.33Fc=0.5 + Cgbo=2.0E-10Cgdo=4.00E-11Cgso=4.00E-11 + Rd=10.0Rs=10.0Rsh=30.0

The “REAL” Data bin/cgiwrap/umosis/swp/params/ibm- 018/t67j_7wl_5lm_ma-params.txt file will serve as the real datahttp:// bin/cgiwrap/umosis/swp/params/ibm- 018/t67j_7wl_5lm_ma-params.txt Save the above file as.lib file. Make changes so as to correspond to the tanner.lib format (You can do this by comparing the format of the library file that you have been using to this new one)

The test setup

The simulation A DC sweep of 100 points of VDS from 0 to 1.8V A Secondary sweep of 10 points of VGS from 0 to 1.8V Include this new file as the library file for simulation Use command.print dc i(MNMOS_1,D) to print NMOS characteristic curve

Analysis and Results Show the I D vs. V DS characteristic for the Mosis transistor data.