Thoughts on C&C hardware modularity. Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no.

Slides:



Advertisements
Similar presentations
XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,
Advertisements

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.
XFEL C+C HARDWARE : REQUIREMENTS 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch.
Μ TCA Crate Timing Receiver Crate Processor 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout Slave FEE 5MHz Clock Trigger.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, MANNHEIM 02 July 2009 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System. 2 OUTLINE June meeting at DESY June meeting at DESY C&C Hardware structure C&C Hardware structure C&C Firmware.
XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.
1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren.
RLH - Spring 1998ECE 611 Hardware - 1 Basic Microprocessor Hardware ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department.
Clock module for TB spring 2012 Uli Schäfer 1 R.Degele, P.Kiese, U.Schäfer, A.Welker Mainz.
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design N. Vinay Krishnan EE249 Class Presentation.
Week 1- Fall 2009 Dr. Kimberly E. Newman University of Colorado.
Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.
Hardware status GOLD Update 02 Feb Uli Schäfer 1.
11/18/2004Comp 120 Fall November 3 classes to go No class on Tuesday 23 November Last 2 classes will be survey and exam review Interconnect and.
1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab.
Using FPGAs with Embedded Processors for Complete Hardware and Software Systems Jonah Weber May 2, 2006.
IEEE-1394 Data Link Design Review Sherry Womack Erik Pace ECE 4040 Dr. Martin Brooke.
1 Daniel Micheletti Darren Allen Daniel Mazo Jon Lamb Lyle Johnson Pixel Perfect WiCam: A Wireless Digital Camera Presented by : Kyle Swenson.
IDE Interface. Objectives In this chapter, you will -Learn about each of the ATA standards (ATA-1 through ATA-6) used in PCs -Identify the ATA connector.
A BRIEF INTRODUCTION TO FIELDBUS 4 hf NETLOGIC PLC TRADITIONAL CABLING SYSTEM TERMINAL BOARD.
SNS Integrated Control System SNS Timing Master LA-UR Eric Bjorklund.
Computer Architecture Lecture10: Input/output devices Piotr Bilski.
CSIS  We need to create some logic to the environment  We want to keep like devices together  We want to make money leasing the use of the space.
Single Board Controller Comments Roger Smith Caltech
J. Christiansen, CERN - EP/MIC
Unit 5 CONTROL CENTERS AND POWER SYSTEM SECURITY.
8086 has 2 interrupt inputs 1. NMI 2. INTR For application where we have interrupts from multiple sources, use an external device called a Priority Interrupt.
MRF & Cosylab on timing system: integration support Joze Dedic the best people make cosylab … Head of Hardware.
11 October 2002Matthew Warren - Trigger Board CDR1 Trigger Board CDR Matthew Warren University College London 11 October 2002.
Ihr Logo Operating Systems Internals & Design Principles Fifth Edition William Stallings Chapter 2 (Part II) Operating System Overview.
Presentation for the Exception PCB February 25th 2009 John Coughlan Ready in 2013 European X-Ray Free Electron Laser XFEL DESY Laboratory, Hamburg Next.
CCD Cameras with USB2.0 & Gigabit interfaces for the Pi of The Sky Project Grzegorz Kasprowicz Piotr Sitek PERG In cooperation with Soltan Institute.
Slide ‹Nr.› l © 2015 CommAgility & N.A.T. GmbH l All trademarks and logos are property of their respective holders CommAgility and N.A.T. CERN/HPC workshop.
NETWORK HARDWARE CABLES NETWORK INTERFACE CARD (NIC)
By Cheyenne Morgan Unit 1- Set up and operate a DAW.
4/19/20021 TCPSplitter: A Reconfigurable Hardware Based TCP Flow Monitor David V. Schuehler.
Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.
11-13th Sept 2007 Calice 1 LDA Protoype Board A Xilinx Spartan board. Will be the basis of a prototype LDA using additional IO boards to interface.
Class-D Garage Band Amplifier Team: Aaron Danielson, Robert Mann, Randall Newcomb, Scott Russell Sponsor: Nigel Thompson Advisor: Dr. William Harrison.
Silberschatz, Galvin and Gagne  Operating System Concepts UNIT II Operating System Services.
Performance of Programmable Logic Devices (PLDs) in read-out of high speed detectors Jack Fried INSTRUMENTATION DIVISION PLD ? PLD ? Muon Tracker PLD Muon.
Connecting EPICS with Easily Reconfigurable I/O Hardware EPICS Collaboration Meeting Fall 2011.
Putting Together a Modular PLC
11 October 2002Paul Dauncey - CDR Introduction1 CDR Introduction and Overview Paul Dauncey Imperial College London.
XFEL In-kind Review Committee Meeting, 11 May 2009 Parliament British Museum XFEL clock and control system In kind contribution proposal Development and.
Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January ISIS1 Testbeam EUDET JRA1 Meeting, DESY 30 th January 2008 Scott Mandry LCFI Collaboration.
Research Unit for Integrated Sensor Systems and Oregano Systems Cern Timing Workshop 2008 Patrick Loschmidt, Georg Gaderer, and Nikolaus Kerö.
What is a Bus? A Bus is a communication system that transfers data between components inside a computer or between computers. Collection of wires Data.
Vertical column Joze Dedic … on behalf of CSL MA team the best people make cosylab.
EtherCAT based RF Interlock System for SwissFEL LLRF 2015 Abstract As part of the overall development effort for SwissFEL's RF and LLRF systems, the RF.
A Time-To-Digital Converter (TDC) Harley Cumming Lisa Kotowski 1.
COP 3503: Programming Fundamentals for CIS Majors 2 Basics.
10/28/09E. Hazen FNAL Workshop1 HCAL DAQ / Timing / Controls Module Eric Hazen, Shouxiang Wu Boston University.
E. Hazen - CMS Electronics Week
Beam Wire Scanner (BWS) serial link requirements and architecture
IAPP - FTK workshop – Pisa march, 2013
Signal Processing for Aperture Arrays
MicroTCA Common Platform For CMS Working Group
Session III Architecture of PLC
CALICE/EUDET Electronics in 2007
Spartan-II + Soft IP = Programmable ASSP
XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,
Control Systems for the APTM and GRID
Presentation transcript:

Thoughts on C&C hardware modularity

Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no need for custom backplane as all boards will have communication built-in MTCA Slave is a bit of a waste of all this... Maybe something more modular … –Generic baseboard with plugins –Master = 1x fanout + 1x TR/beam interfaces plug-in –Slave = 2x fanout

TCP/IP Local AMC Control Fanout 8 Plug-in CC Master To FEE FPGA Master Plug-in TR/ Machine etc. Signals PLL etc Vertical Plugins (double stack conn.)

Layered plugins (single stack conn.) TCP/IP Local AMC Control Fanout 8 Plug-in To TR or CC Master To FEE FPGA Master Plug-in PLL etc

More Thoughts Multiple plug-ins nice as all fanouts are equal (delays etc.) BUT a C&C baseboard with 8x fanout integrated has other advantages: –Basic unit of the C&C system is one board –Cheaper Maybe play the same PCB but load only the parts required … –Larger FPGA (more logic/IO) on Master