1  Modified from  1998 Morgan Kaufmann Publishers Chapter 2: Instructions: Language of the Machine citation and following credit line is included: 'Copyright 1998 Morgan Kaufmann Publishers.' Permission is granted to alter and distribute this material provided that the following credit line is included: 'Adapted from Computer Organization & Design, The hardware/Software Interface, Patterson and Hennesy, second edition, Copyright 1998 Morgan Kaufmann Publishers.' " This material may not be copied or distributed for commercial purposes without express written permission of the copyright holder.

2  Modified from  1998 Morgan Kaufmann Publishers Instructions: Language of the Machine Introduction ISA Classes (Instruction Set Architecture) Addressing Instruction Formats MIPS Instruction Set Architecture (ISA) –Instruction Types Arithmetic Data Transfer Conditionals Branch –Addressing Modes Alternative Architectures –RISC vs. CISC PowerPC Intel 80X86

3  Modified from  1998 Morgan Kaufmann Publishers Introduction Our goal is to understand how a computer works by studying how programs are represented at the machine level and how they are executed. We will study a simple assembly language, MIPS, and use it throughout this course for our study of computer architecture. A program to be executed on a computer consists of a number of instructions that are stored in the main memory. An instruction consists of a number of bits. Instructions of a specific machine have a defined format where each subset of bits will be interpreted to cause some action to take place.

4  Modified from  1998 Morgan Kaufmann Publishers Introduction continues How Does a computer work? A computer system normally consists of several components Proc Caches Busses Memory I/O Devices: Controllers adapters Disks Displays Keyboards Networks

5  Modified from  1998 Morgan Kaufmann Publishers Introduction continues Instructions are fetched from memory and are placed in a special register, Instruction register or IR, in the CPU where they are decoded and executed. When you start your computer, it repeatedly executes a hardware loop called the “Fetch & Execute” cycle. Lets look at a simple fetch & execute cycle to better understand its function.

6  Modified from  1998 Morgan Kaufmann Publishers Introduction continues Fetch & Execute Cycle Repeat IR  M[pc] ; fetch: load the instruction register with the instruction stored in memory at address pointed to by the program counter, pc. Increment pc ;increment pc to point to the next instruction to be fetch at the next cycle. Decode IR ; Calculate effective address of operand(s) ; Fetch operand(s); Execute(IR) ;execute the instruction Until IR = machine halt

7  Modified from  1998 Morgan Kaufmann Publishers Introduction continues In this course, it is expected that you have knowledge of assembly language and are familiar with its concepts. Please review Chapter 2 in depth to make sure you are comfortable with the important concepts. Here we will review and highlight some of the features we will need toward the design of a simple MIPS computer. To start on the computer architecture design, we will relate the assembly language, in this case MIPS, to machine level language which is what the computer hardware is designed to understand. But first an overview of major features!

8  Modified from  1998 Morgan Kaufmann Publishers Basic ISA Classes The ISA’s can be classified based on the number and type of operands that a machine instruction uses. The main classifications are: –Accumulator: where one operand comes from memory and the other is always the accumulator register in the processor. –Stack: where all operations are performed with the two top elements of the stack, and stack operations push and pop. –General Purpose Registers, GPR: This can be two-address or three-address register machine. All operations are performed using two or three registers respectively.

9  Modified from  1998 Morgan Kaufmann Publishers Basic ISA Classes continued Accumulator (1 register): 1 addressadd Aacc  acc + mem[A] 1+x addressaddx Aacc  acc + mem[A + x] Stack: 0 addressaddtos  tos + next General Purpose Register: 2 addressadd A BEA(A)  EA(A) + EA(B) 3 addressadd A B CEA(A)  EA(B) + EA(C) Load/Store: 3 addressadd Ra Rb RcRa  Rb + Rc load Ra RbRa  mem[Rb] store Ra Rbmem[Rb]  Ra Comparison: Bytes per instruction? Number of Instructions? Cycles per instruction?

10  Modified from  1998 Morgan Kaufmann Publishers Basic ISA Classes continued

11  Modified from  1998 Morgan Kaufmann Publishers General Purpose Registers Dominate ° all machines use general purpose registers °Advantages of registers registers are faster than memory registers are easier for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack registers can hold variables -memory traffic is reduced, so program is sped up (since registers are faster than memory) -code density improves (since register named with fewer bits than memory location)

12  Modified from  1998 Morgan Kaufmann Publishers Summary on Instruction Classes Expect new instruction set architecture to use general purpose register Pipelining => Expect it to use load store variant of GPR ISA

13  Modified from  1998 Morgan Kaufmann Publishers Example: MIPS I Registers Programmable storage –2^32 x bytes of memory –31 x 32-bit GPRs (R0 = 0) –32 x 32-bit FP regs (paired DP) –HI, LO, PC DP: double precision

14  Modified from  1998 Morgan Kaufmann Publishers Memory Addressing °Since 1980 almost every machine uses addresses to level of 8-bits (byte) °2 questions for design of ISA: Since we could read a 32-bit word as four loads of bytes from sequential byte addresses or as one load of word from a single byte address, how do byte addresses map onto words? Can a word be placed on any byte boundary?

15  Modified from  1998 Morgan Kaufmann Publishers Addressing Objects: Endianess and Alignment Big Endian: address of most significant byte = word address (xx00 = Big End of word) –IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian:address of least significant byte = word address (xx00 = Little End of word) –Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msblsb little endian byte big endian byte 0 Alignment: require that objects fall on address that is multiple of their size Aligned Not Aligned

16  Modified from  1998 Morgan Kaufmann Publishers Addressing Modes Addressing modeExampleMeaning RegisterAdd R4,R3R4  R4+R3 ImmediateAdd R4,#3R4  R4+3 DisplacementAdd R4,100(R1)R4  R4+Mem[100+R1] Register indirectAdd R4,(R1)R4  R4+Mem[R1] Indexed / BaseAdd R3,(R1+R2)R3  R3+Mem[R1+R2] Direct or absoluteAdd R1,(1001)R1  R1+Mem[1001] Memory indirectAdd  R1+Mem[Mem[R3]] Auto-incrementAdd R1,(R2)+R1  R1+Mem[R2]; R2  R2+d Auto-decrementAdd R1,–(R2)R2  R2–d; R1  R1+Mem[R2] Scaled Add R1,100(R2)[R3]R1  R1+Mem[100+R2+R3*d] Why Auto-increment/decrement? Scaled?

17  Modified from  1998 Morgan Kaufmann Publishers Addressing Mode Usage? (ignore register mode) 3 programs measured on machine with all address modes (VAX) --- Displacement: 42% avg, 32% to 55% 75% --- Immediate: 33% avg, 17% to 43% 85% --- Register deferred (indirect): 13% avg, 3% to 24% --- Scaled: 7% avg, 0% to 16% --- Memory indirect: 3% avg, 1% to 6% --- Misc:2% avg, 0% to 3% 75% displacement & immediate 88% displacement, immediate & register indirect

18  Modified from  1998 Morgan Kaufmann Publishers Displacement Address Size? ° Avg. of 5 SPECint92 programs v. avg. 5 SPECfp92 programs ° Most addresses > 2 3 (8) and  2 4 (16) °1% of addresses > 16-bits ° bits of displacement needed Address Bits

19  Modified from  1998 Morgan Kaufmann Publishers Immediate Size? 50% to 60% fit within 8 bits 75% to 80% fit within 16 bits

20  Modified from  1998 Morgan Kaufmann Publishers Addressing Summary Data Addressing modes that are important: Displacement, Immediate, Register Indirect Displacement size should be 12 to 16 bits Immediate size should be 8 to 16 bits

21  Modified from  1998 Morgan Kaufmann Publishers Generic Examples of Instruction Format Widths Variable: Fixed: Hybrid: … …

22  Modified from  1998 Morgan Kaufmann Publishers Summary of Instruction Formats If code size is most important, use variable length instructions If performance is most important, use fixed length instructions Recent embedded machines (ARM, MIPS) added optional mode to execute subset of 16-bit wide instructions (Thumb, MIPS16); per procedure decide performance or density

23  Modified from  1998 Morgan Kaufmann Publishers Instruction Format If have many memory operands per instructions and many addressing modes, =>Address Specifier per operand If have load-store machine with 1 address per instr. and one or two addressing modes, => encode addressing mode in the opcode

24  Modified from  1998 Morgan Kaufmann Publishers Typical Operations (little change since 1960) Data MovementLoad (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Arithmeticinteger (binary + decimal) or FP Add, Subtract, Multiply, Divide Logicalnot, and, or, set, clear Shiftshift left/right, rotate left/right Control (Jump/Branch)unconditional, conditional Subroutine Linkagecall, return Interrupttrap, return Synchronizationtest & set (atomic r-m-w) Stringsearch, translate Graphics (MMX)parallel subword ops (4 16bit add)

25  Modified from  1998 Morgan Kaufmann Publishers Top 10 80x86 Instructions

26  Modified from  1998 Morgan Kaufmann Publishers Operation Summary Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return;