© 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

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Presentation transcript:

© 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA Platforms, 2005 Kerry Veenstra Workshop on Architecture Research using FPGA Platforms, 2005

© 2005 Altera Corporation Altera’s SOPC Builder Supports Rapid System Prototyping Performs the Mundane Tasks of System Integration Allows Focus on the System Architecture Generates Verilog & VHDL Systems That Run on ModelSim and FPGAs  Generated Interconnect is Correct by Design

© 2005 Altera Corporation Embedded System Integration Processor (Bus Master) 32-Bit

© 2005 Altera Corporation Embedded System Integration Processor (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit

© 2005 Altera Corporation Embedded System Integration Address Processor (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit

© 2005 Altera Corporation Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit

© 2005 Altera Corporation Data Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit

© 2005 Altera Corporation Data Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit Width-Match

© 2005 Altera Corporation Data Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Interrupt Controller Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit Width-Match

© 2005 Altera Corporation Data Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Interrupt Controller Address Data Ethernet (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit Width-Match

© 2005 Altera Corporation Data Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Interrupt Controller Address Data Ethernet (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit Arbiter Width-Match

© 2005 Altera Corporation Data Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Interrupt Controller Address Data Ethernet (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit Arbiter Width-Match Clock 1Clock 2

© 2005 Altera Corporation Data Embedded System Integration Address Address Decoder Processor (Bus Master) 32-Bit Interrupt Controller Address Data Ethernet (Bus Master) 32-Bit Slave 3 16-Bit Slave 1 8-Bit Slave 5 64-Bit Slave 4 32-Bit Slave 2 32-Bit Arbiter Bus Interface Designed Manually

© 2005 Altera Corporation SOPC Builder Integration Processor (Bus Master) 32-Bit Ethernet (Bus Master) 32-Bit

© 2005 Altera Corporation SOPC Builder Integration Processor (Bus Master) 32-Bit Ethernet (Bus Master) 32-Bit Slave 1 8-Bit Slave 2 32-Bit Slave 3 16-Bit Slave 4 32-Bit Slave 5 64-Bit

© 2005 Altera Corporation Width-Match Interrupt Controller Address Decoder Arbiter Width-Match Arbiter Width-Match Arbiter Width-Match Arbiter Width-Match Arbiter SOPC Builder- Generated Avalon™ Switch Fabric Wait-State Generation Data Multiplexing SOPC Builder Integration Processor (Bus Master) 32-Bit Ethernet (Bus Master) 32-Bit Slave 1 8-Bit Slave 2 32-Bit Slave 3 16-Bit Slave 4 32-Bit Slave 5 64-Bit

© 2005 Altera Corporation Development Board SOPC Builder: Design Flow 17 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Development Board SOPC Builder & IDE 18 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Development Board Targets: ModelSim & FPGA 19 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Development Board SOPC Builder System Editor 20 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation SOPC Builder System Editor

© 2005 Altera Corporation SOPC Builder System Editor Component

© 2005 Altera Corporation SOPC Builder System Editor Connection Panel Component

© 2005 Altera Corporation SOPC Builder System Editor Address Map Connection Panel Address Map Component

© 2005 Altera Corporation SOPC Builder System Editor IRQ Priorities Address Map Clock Domains Connection Panel Address Map Component

© 2005 Altera Corporation Development Board Import HDL (Optional) 26 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Development Board Generate HDL and C/C++ Headers 27 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Development Board Compile Software & Run on ModelSim 28 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Development Board Development Board Compile HDL into FPGA 29 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Development Board Development Board Compile Software & Run on FPGA 30 Verilog or VHDL Quartus II Integrated Development Environment System Description SOPC Builder ModelSim C/C++ Header per Master GenerateImport SOF Hex Debug

© 2005 Altera Corporation Component Interface

© 2005 Altera Corporation Width-Match Interrupt Controller Address Decoder Arbiter Width-Match Arbiter Width-Match Arbiter Width-Match Arbiter Width-Match Arbiter SOPC Builder- Generated Avalon™ Switch Fabric Wait-State Generation Data Multiplexing SOPC Builder Component Interface Processor (Bus Master) 32-Bit Ethernet (Bus Master) 32-Bit Slave 1 8-Bit Slave 2 32-Bit Slave 3 16-Bit Slave 4 32-Bit Slave 5 64-Bit

© 2005 Altera Corporation Avalon SOPC Builder Component Interface Processor (Bus Master) 32-Bit Ethernet (Bus Master) 32-Bit Slave 1 8-Bit Slave 2 32-Bit Slave 3 16-Bit Slave 4 32-Bit Slave 5 64-Bit

© 2005 Altera Corporation Dynamic Port Connections Avalon Port Types reset chipselect address byteenable read readdata write writedata data waitrequest readyfordata dataavailable datavalid flush begintransfer endofpacket irq irqnumber clk resetrequest All Signals Available In Negative Form Avalon Port Types reset chipselect address byteenable read readdata write writedata data waitrequest readyfordata dataavailable datavalid flush begintransfer endofpacket irq irqnumber clk resetrequest All Signals Available In Negative Form Avalon Is a Superset of Bus Interfaces  ISA, Wishbone Many Port Types Supported  Peripheral Uses Only the Ports It Needs Any Combination of Ports Is Possible  Avalon Switch Logic Controls Signal Timing Supports Arbitrary Setup Time, Hold Time & Wait States Simplifies Peripheral Design

© 2005 Altera Corporation Traditional Buses: Master Arbitration System CPU (Master 1) I/O 1 Program Memory Slaves Shared Bus Data Memory Arbiter Data Memory DSP (Master 2) I/O 1 Masters Slaves I/O CPU (Master 3) I/O 3 Program Memory Data Memory Custom Accelerator Peripheral System Bottleneck

© 2005 Altera Corporation SOPC Builder: Slave-Side Arbitration System CPU (Master 1) I/O 1 Program Memory Slaves Data Memory Arbiter Data Memory Aribiter DSP (Master 2) I/O 1 Masters Slaves Switch Fabric I/O CPU (Master 3) I/O 3 Program Memory Data Memory Arbiter Custom Accelerator Peripheral

© 2005 Altera Corporation SOPC Builder: Slave-Side Arbitration System CPU (Master 1) I/O 1 Program Memory Slaves Data Memory Arbiter Data Memory Aribiter DSP (Master 2) I/O 1 Masters Slaves Switch Fabric I/O CPU (Master 3) I/O 3 Program Memory Data Memory Arbiter Simultaneous Operation for All Masters Custom Accelerator Peripheral

© 2005 Altera Corporation Altera’s SOPC Builder Supports Rapid System Prototyping Performs the Mundane Tasks of System Integration Allows Focus on the System Architecture Generates Verilog & VHDL Systems That Run on ModelSim and FPGAs  Generated Interconnect is Correct by Design

© 2005 Altera Corporation System Interconnect Connecting Masters & Slaves Dynamic Bus Sizing Master Arbiter Master Clock Domain Xing Streaming Master Arbiter Latency Slave Arbiter 32-bit 16-bit Clock 1 Clock 2