Low Power Architecture and Implementation of Multicore Design Khushboo Sheth, Kyungseok Kim Fan Wang, Siddharth Dantu ELEC6270 Low Power Design of Electronic Circuits Team Project VLSI D&T Seminar Nov Advisor: Dr. V Agrawal

Project Objectives  Design and verify 16-bit ALU with synchronous clocked inputs and outputs.  Study low-voltage power and delay characteristics of the design.  Redesign ALU for minimum power and highest speed.

Component of Power Dissipation  Dynamic  Power due to Signal transitions. Logic power (due to logic transitions). Logic power (due to logic transitions). Glitch power (due to glitches). Glitch power (due to glitches).  Short Circuit power  Static  Leakage power (due to leakage currents).

Power components in CMOS circuit V DD Ground CLCL R on R=large v i (t) v o (t) Dynamic power Short circuit power Leakage power Power =CV DD 2

1-bit ALU Design 1-bit ALU Core Reg B Reg A Reg C

1 bit ALU Core Simulation Specification Technology TSMC 0.25 um Application Voltage 2.5 Volt N-MOS Vth V P-MOS Vth V Temperature 90 C degree Spice Simulator Eldo ver Sweep Supply Voltage (6 point) 0,0.5,1.0,1.5,2.0,2.5 V

Combinational Logic DFF NX156 NX80 NX16 NX60 A B CLK C CYIN CY Z 1-bit ALU Core Timing ( Vdd=2.5V ) Longest Path in Combinational Logic: c <= a+b (Opcode 0000) opcode[3:0] COMPOUT C CY COMPOUT Z opcode 1010 (nand) opcode 1001 (c<=b) opcode 1000 (c<=a) opcode 0111 (and) opcode 0110 (or) opcode 0101 (nor) opcode 0100 (xor) opcode 0011 (not equal) opcode 0010 (equal) opcode 0001 (a-b) opcode 0000 (a+b) opcode others (all zero’s output)

1-bit ALU Core Sweep Vdd from 2.5V to 0V 2.5V 2.0V 1.5V 1.0V 0.5V 0.0V Analog Mode C(NX156) Output Vdd=2.5 Vdd=0.5

1Bit ALU Core Logic Operation Supply Voltage Sweep near PMOS Vth = V ( ver. NMOS Vth= 0.365) Sweep From Vsupply = 0.50 to 1.00 Volt ( linear increment 0.05 V, 11 point) Vsupply = 0.85 V Correct Operation Overshoot Ripples Vsupply = 0.85 V (Analog Domain) Output Input Vsupply = 0.80 V (Analog Domain) Vsupply = 0.80 V Wrong Operation Output Input opcode 1000 (c<=a)

1-bit ALU Average Power vs. 1-bit ALU Core Average Power 1bit ALU Block Average Power 1-bit ALU Core Delay Power = CV DD 2

16 Bit ALU (Single Core) Design Combinational Logic (16-Bit ALU) Output Input Register CK Supply voltage= V ref Total capacitance switched per cycle= C ref Clock frequency= f Power consumption:P ref = C ref V ref 2 f C ref

16-BIT ALU Vectors abOpcodecyin Vector (sub) 0 Vector (comp) 0 Vector (xor) 0 Vector (add) 0 Vector (nand) 0 Vector (sub) 0 *Vector4 activate the critical path, carryout = 1

16-Bit ALU Simulation Result Circuit information: # 694 Gates Clock Frequency applied: 10 MHz Temperature: 27C o Vectors Applied: 6 vectors TSMC025 Technology : Vthn = V, Vthp = V Simulation Time: 700 ns By ELDO, SPICE simulation Simulation Time: 700 ns Voltage (v) (v) Static Power(nw) Average Power (uw) Delay (ns) Ckt failed

16 Bit ALU Functional Correct Operation at 2.5 V, 1.25 V, 0.85 V and V for 6 Vectors

Circuit V (< Vth) Circuit V (< Vth) Simulated Single Vector Pair

16-Bit ALU Power Savings and Delay Increase with 2.5 Volts Voltage (v) (v)(Reference)VDD 2.5V 2.5V 1.25 V VDD/2 VDD/ V VDD/3 VDD/ V VDD/4 VDD/4 Average Power (uw) P2.5/6.2484% P2.5/ % P2.5/ % Delay (ns) *D *D *D2.5

16 Bit ALU Power Savings and Delay Increase with Volts Voltage(v)(Reference) (VDD/1.5)0.625(VDD/2) Average Power (uw) P1.25/2.3557%14.67P1.25/4.2777% Delay(ns) * D * D1.25

Different Technology Impact On Power Saving 16 Bit ALU Simulation Setup:  Supply Voltage: 2.5v  Simulation Transient Time: 700 ns  6 vectors  Temperature: 27C o TechnologyTSMC035TSMC025 #Gates after synthesis 734 gates 694 gate Voltage 2.5 V Static Power N Watts N Watts Average Power U Watts U Watts Delay 3.12 ns 2.83 ns

Temperature Influence On Power  734  Circuit information: # 734 Gates   Clock Frequency applied: 10 MHz ; Vdd=2.5V  Vectors Applied: 6 vectors  Simulation Time: 700 ns   TSMC035 Technology Temperature (C o ) Static Power (nw) (nw) mw Average Power (uw) w Delay (ns) Ckt fail!!

Multicore Design Methodology  Lower supply voltage This slows down circuit speed This slows down circuit speed Use parallel computing to gain the speed back Use parallel computing to gain the speed back  Multi-core means to place two or more complete cores within a single module.  This architecture is a “divide and conquer” strategy. By splitting the work between multiple execution cores, a multi-core design can perform more work within a given clock cycle.  About more than 60% reduction in power is observed. Source:

Parallel Architecture Comb. Logic Copy 1 Comb. Logic Copy 2 Comb. Logic Copy 4 Rgst Register Rgst 4 to 1 multiplexer Input Output CK f f/4 Rgst f/4 Comb. Logic Copy 3 f/4 Mux control Ck0 Ck1 Ck2 Ck3 16 Bit ALU

Control Signals, N = 4 CK Phase 1 Phase 2 Phase 3 Phase 4 Mux control ……

16 Bit ALU Multi-core Power Savings and Delay Increase with Volts 16 Bit ALU Multi-core Power Savings and Delay Increase with Volts Temperature: 27C Vectors Applied: 6 vectors Circuit information: # 2617 Gates Clock Frequency applied: 10 MHz Temperature: 27C Vectors Applied: 6 vectors TSMC025 Technology : Vthn = V, Vthp = V Simulation Setup: Simulation Time: 700 ns Simulator: ELDO(Spice) Simulation Setup: Simulation Time: 700 ns Voltage (v) (v)(Reference) VDD/20.85VDD/30.625VDD/40.45 Static Power (nw) Average Power (uw) UP2.5/7.1986%40.93UP2.5/16.894%21.13UP2.5/ %7.26U Delay(ns) *D *D *D2.5 Ckt failed

16 Bit ALU Multicore Power Savings and Delay Increase with Volts Voltage(v) (Reference) (Reference)1.25 VDD VDD0.85VDD/ VDD/2 Average Power (uw) P1.25/2.3357%21.13P1.25/4.5278% Delay(ns) * D * D1.25

Power and Delay V Reference Design with Multicore Design at different voltages Voltage(v)2.5VDD Reference Design 1.25 Multicore Design VDD/ Multicore Design VDD/30.725MulticoreDesignVDD/3.50.7MulticoreDesignVDD/ Multicore Design VDD/4 Average Power (uw) P2.5/4.0976%40.93P2.5/ %25.6P2.5/ %22.35P2.5/ %21.14P2.5/ % Delay(ns) D2.5/ D2.5/ D2.5/ D2.5/ D2.5/0.09

Summary  For Single core ALU design we get more than 60% power savings at reduced voltage but at the cost of performance.  With Reference of 2.5 Volts we observe power drops faster than 1/Vsquare.  With Reference of 1.25 Volts, power drop is almost equal to 1/Vsquare.  Multi-core design helps to gain the speed back at reduced voltage and consumes less power.

References  ELEC6270 Low Power Design Electronics Class Slides from Dr. Agrawal  Spring 06, Dr. Agrawal’ Presentation on VLSI D&T seminar “Multi-Core Parallelism for Low-Power Design” Multi-Core Parallelism for Low-Power DesignMulti-Core Parallelism for Low-Power Design   N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts, Addison-Wesley,  L. Shang, R.P Dick, “Thermal crisis: challenges and potential solutions,” Potentials IEEE, vol. 25, Issue 5, 2006  International Technology Roadmap for Semiconductors.  Alokik Kanwal, “A review of Carbon Nanotube Field Effect Transistors” Version 2.0, 2003  K. K Likharev, “Single Electron Devices and their applications,” Proc IIEEE, vol. 87, no. 4, pp , Apr  A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers (Now Springer),  “Quad-core processor forecas”,Alexander Alexander WolfeTechWebAlexander WolfeTechWeb

Thank You !!!