CMPUT 429/CMPE Computer Systems and Architecture1 CMPUT429 - Winter 2002 Topic5: Memory Technology José Nelson Amaral

CMPUT 429/CMPE Computer Systems and Architecture2 Address Decoding F FFFFF Bank F F7FFF Bank E EFFFF Bank E E7FFF Bank 0

CMPUT 429/CMPE Computer Systems and Architecture3 Address Decoding on a Microprocessor System A0 A1 A14 O0 O1 O7 CS OE A0 A1 A14 D0 D1 D7 D0 D1 D7 A0 A1 A19 A0 A1 A14 O0 O1 O7 CS OE A0 A1 A14 D0 D1 D7 A0 A1 A14 O0 O1 O7 CS OE A0 A1 A14 D0 D1 D7 A0 A1 A14 O0 O1 O7 CS OE A0 A1 A14 D0 D1 D7 SE0000_L SE8000_L SF0000_L SF8000_L A19 A18 A17 A15 A16 HIMEN_L 1Y0 1Y1 1Y2 1Y3 1G 1A 1B A0 A1 A19 D0 D1 D7 READ WRITE 74x139 microprocessor 27256

CMPUT 429/CMPE Computer Systems and Architecture4 Types of Memories Read/Write Memory (RWM): the time required to read or write a bit of memory is independent of the bit’s location once a word is written to a location, it remains stored as long as power is applied to the chip, unless the location is written again. the data stored at each location must be refreshed periodically by reading it and then writing it back again, or else it disappears we can store and retrieve data Random Access Memory (RAM): Static Random Access Memory (SRAM): Dynamic Random Access Memory (DRAM):

CMPUT 429/CMPE Computer Systems and Architecture5 Random Access Memories (RAMs) A Random-Access Memory (RAM) is so called to contrast with its predecessor, the Serial-Access Memory. In a serial access memory, memory positions become available for reading on a sequential fashion. Therefore to read an specific memory position, the reader must wait a variable time delay for the memory position to became available. In principle, in a RAM, all positions of the memory can be read on a random fashion with approximately the same delay for all positions. However, modern RAMs allow burst accesses that favor sequential accesses (complete them in less time).

CMPUT 429/CMPE Computer Systems and Architecture6 Static-RAM Control Inputs The outputs of memory chips are often connected to a three-state bus, a bus that can be driven by many devices. Therefore each memory chip should drive the bus only when commanded to do so by the control logic. Output Enable (OE): Enable the output into the data lines Chip Select (CS): Used in connection with OE to simplify the design of a multiple chip system. Write Enable (WE): When asserted, the data inputs are written to the selected memory location. The following control inputs are typically used to control a Static-RAM.

CMPUT 429/CMPE Computer Systems and Architecture7 A 2 n  b SRAM Address inputs A n-1 A0A0 A1A1 Data inputs DIN b-1 DIN 0 DIN 1 control inputs CS OE WE Data outputs DOUT b-1 DOUT 0 DOUT 1 2 n  b SRAM

CMPUT 429/CMPE Computer Systems and Architecture8 SRAMs (Static Random Access Memories) A0 A1 A12 IO0 IO1 IO7 OE CS1 A0 A1 A12 D0 D1 D HM6264 WE CS2 A0 A1 A14 IO0 IO1 IO7 OE WE A0 A1 A14 D0 D1 D HM62256 CS A0 A1 A16 IO0 IO1 IO7 OE CS1 A0 A1 A16 D0 D1 D HM WE CS2 A0 A1 A18 IO0 IO1 IO7 OE WE A0 A1 A18 D0 D1 D HM CS

CMPUT 429/CMPE Computer Systems and Architecture9 Accesses to SRAM Read An address is placed on the address inputs while CS and OE are asserted. The latch outputs for the selected memory locations are delivered to DOUT. Write An address is placed on the address inputs and a data word is placed on DIN; then CS and WE are asserted. The latches in the selected memory location open, and the input word is stored.

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3DOUT2DOUT1DOUT0 3-to-8 decoder A2 A1 A DIN3DIN0DIN2DIN1 WE_L CS_L OE_L WR_L IOE_L

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder A2 A1 A DIN3 WE_L CS_L OE_L WR_L IOE_L

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder A2 A1 A DIN3 WE_L CS_L OE_L WR_L IOE_L

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder A2 A1 A DIN3 WE_L CS_L OE_L WR_L IOE_L

CMPUT 429/CMPE Computer Systems and Architecture14 SRAM with Bi-directional Data Bus IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DIO3DIO2DIO1DIO0 WE_L CS_L OE_L WR_L IOE_L microprocessor

CMPUT 429/CMPE Computer Systems and Architecture15 Internal Address Decoding To avoid high complexity in the decoding logic, all memories (EPROMs, SRAMs, and DRAMs) use two-dimensional decoding which reduces the decoder size to approximately the square root of the number of addresses. The memory cells are organized in a two-dimensional array. Some address lines are used to select a row and the others are used to select a column. The cell selected by the whole address is at the intersection of the row and the column.

CMPUT 429/CMPE Computer Systems and Architecture16 Static-RAM Read Timing t AA (access time for address): how long it takes to get stable output after a change in address. t ACS (access time for chip select): how long it takes to get stable output after CS is asserted. t OE (output enable time): how long it takes for the three-state output buffers to leave the high-impedance state when OE and CS are both asserted. t OZ (output-disable time): how long it takes for the three-state output buffers to enter high-impedance state after OE or CS are negated. t OH (output-hold time): how long the output data remains valid after a change to the address inputs.

CMPUT 429/CMPE Computer Systems and Architecture17 Static-RAM Read Timing stable valid t AA t OZ  t AA t OE t ACS t OZ t OE Max(t AA, t ACS ) t OH ADDR CS_L OE_L DOUT WE_L = HIGH

CMPUT 429/CMPE Computer Systems and Architecture18 Static-RAM Write Timing t AS (address setup time before write): all address inputs must be stable at this time before both CS and WE are asserted. t AH (address hold time after write): all address inputs must be held stable until this time after CS or WE is negated. t CSW (chip-select setup before end of write): CS must be asserted at least this long before the end of the write cycle. t WP (write pulse width): WE must be asserted at least this long to reliably latch data into the selected cell. t DH (data hold time after the end of write): All data inputs must be held stable until this time after the write cycle ends. t DS (data setup time before end of write): All of the data inputs must be stable at this time before the write cycle ends.

CMPUT 429/CMPE Computer Systems and Architecture19 Dynamic Memory Cell An SRAM cell has a bi-stable latch that requires from four to six transistors to be built. To deliver the higher memory density required for computer systems, a single transistor memory cell was developed. 1-bit DRAM cell word line bit line

CMPUT 429/CMPE Computer Systems and Architecture20 Writing 1 in a Dynamic Memories To store a 1 in this cell, a HIGH voltage is placed on the bit line, causing the capacitor to charge through the on transistor. 1-bit DRAM cell word line bit line

CMPUT 429/CMPE Computer Systems and Architecture21 Writing 0 in a Dynamic Memories To store a 0 in this cell, a LOW voltage is placed on the bit line, causing the capacitor to discharge through the on transistor. 1-bit DRAM cell word line bit line

CMPUT 429/CMPE Computer Systems and Architecture22 Destructive Reads To read the DRAM cell, the bit line is precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. Depending on the charge in the capacitor, the precharged bit line is pulled slightly higher or lower. A sense amplifier detects this small change and recovers a 1 or a 0. 1-bit DRAM cell word line bit line

CMPUT 429/CMPE Computer Systems and Architecture23 Recovering from Destructive Reads The read operation discharges the capacitor. Therefore a read operation in a dynamic memory must be immediately followed by a write operation of the same value read to restore the capacitor charges. 1-bit DRAM cell word line bit line

CMPUT 429/CMPE Computer Systems and Architecture24 Forgetful Memories The problem with this cell is that it is not bi-stable: only the state 0 can be kept indefinitely, when the cell is in state 1, the charge stored in the capacitor slowly dissipates and the data is lost. 1-bit DRAM cell word line bit line

CMPUT 429/CMPE Computer Systems and Architecture25 Refreshing the Memory Vcap 0V HIGH LOW V CC time 0 stored 1 written refreshes The solution is to periodically refresh the memory cells by reading and writing back each one of them.

CMPUT 429/CMPE Computer Systems and Architecture26 Internal Structure of a 64K  1 DRAM Row decoder 256  256 array Column latches, multiplexers, and demultiplexers control RAS_L CAS_L WE_L A0-A7 column address latch, mux, and dmux control row address DOUT DIN

Step 1: Apply row address 1 Step 2: RAS go from high to low and remain low 2 Step 4: WE must be high 4 Step 3: Apply column address 3 Step 5: CAS goes from high to low and remain low 5 Step 6: OE goes low 6 Step 7: Data appears 7 Step 8: RAS and CAS return to high 8 Read Cycle on an Asynchronous DRAM

Write Cycle on an Asynchronous DRAM

CMPUT 429/CMPE Computer Systems and Architecture29 Improved DRAMs Central Idea: Each read to a DRAM actually reads a complete row of bits or word line from the DRAM core into an array of sense amps. A traditional asynchronous DRAM interface then selects a small number of these bits to be delivered to the cache/microprocessor. All the other bits already extracted from the DRAM cells into the sense amps are wasted.

CMPUT 429/CMPE Computer Systems and Architecture30 Fast Page Mode DRAMs In a DRAM with Fast Page Mode, a page is defined as all memory addresses that have the same row address. To read in fast page mode, all the steps from 1 to 7 of a standard read cycle are performed. Then OE and CAS are switched high, but RAS remains low. Then the steps 3 to 7 (providing a new column address, asserting CAS and OE) are performed for each new memory location to be read.

A Fast Page Mode Read Cycle on an Asynchronous DRAM

CMPUT 429/CMPE Computer Systems and Architecture32 Enhanced Data Output RAMs (EDO-RAM) The process to read multiple locations in an EDO-RAM is very similar to the Fast Page Mode. The difference is that the output drivers are not disabled when CAS goes high. This distintion allows the data from the current read cycle to be present at the outputs while the next cycle begins. As a result, faster read cycle times are allowed.

An Enhanced Data Output Read Cycle on an Asynchronous DRAM

CMPUT 429/CMPE Computer Systems and Architecture34 Synchronous DRAMs (SDRAM) A Synchronous DRAM (SDRAM) has a clock input. It operates in a similar fashion as the fast page mode and EDO DRAM. However the consecutive data is output synchronously on the falling/rising edge of the clock, instead of on command by CAS. How many data elements will be output (the length of the burst) is programmable up to the maximum size of the row. The clock in an SDRAM typically runs one order of magnitude faster than the access time for individual accesses.

CMPUT 429/CMPE Computer Systems and Architecture35 SDRAM Burst Read Cycle

CMPUT 429/CMPE Computer Systems and Architecture36 DDR SDRAM A Double Data Rate (DDR) SDRAM is an SDRAM that allows data transfers both on the rising and falling edge of the clock. Thus the effective data transfer rate of a DDR SDRAM is two times the data transfer rate of a standard SDRAM with the same clock frequency.

CMPUT 429/CMPE Computer Systems and Architecture37 The Rambus DRAM (RDRAM) Multiple memory arrays (banks) Rambus DRAMs are synchronous and transfer data on both edges of the clock.

CMPUT 429/CMPE Computer Systems and Architecture38 SDRAM Memory Systems Complex circuits for RAS/CAS/OE. Each DIMM is connected in parallel with the memory controller. (DIMM = Dual In-line Memory Module) Often requires buffering. Needs the whole clock cycle to establish valid data. Making the bus wider is mechanically complicated.

CMPUT 429/CMPE Computer Systems and Architecture39 RDRAM Memory Systems

CMPUT 429/CMPE Computer Systems and Architecture40 Internal RDRAM Organization

CMPUT 429/CMPE Computer Systems and Architecture41 RDRAM Banks  SDRAM Banks

CMPUT 429/CMPE Computer Systems and Architecture42 Further Reading To learn more about the differences between SDRAM systems and Rambus DRAM systems for personal computers, visit these websites: Crisp, Richard, “Direct Rambus Technology: The New Main Memory Standard,” IEEE Micro, 17(6): 18-28, Nov/Dec, 1997.