ICCD Conversion Driven Design of Binary to Mixed Radix Circuits Ashur Rafiev, Julian Murphy, Danil Sokolov, Alex Yakovlev School of EECE, Newcastle University, UK {ashur.rafiev, j.p.murphy, danil.sokolov, ncl.ac.uk

ICCD Outline  Switching Balanced Codes Conversion Driven Design (CDD) Motivation Conversion Basics Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results Conclusions Outline

ICCD Switching Balanced Codes M-of-N data encoding: data signal is represented with N wires M of them are active (high) Return-to-zero (RTZ) protocol: data signals are separated with dummy signals (spacers) Application areas: Security Asynchronous system design Network-on-chip communication Switching Balanced Codes

ICCD of-2 (Dual-Rail) and 1-of-4 Encodings multi-valuedsingle-rail (binary) dual-rail1-of NULLspacer

ICCD Outline  Switching Balanced Codes  Conversion Driven Design Motivation Conversion Basics Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results Conclusions Outline

ICCD Conversion Driven Design: Motivation + Higher radix signals consume less power and reduce cross- talk effect – Require multi-valued logic synthesis + Some tools and techniques already exist (e.g. MV-SIS) – Moving away from the RTL design flow is frequently frowned upon by industry  Reuse existing popular design tools for multi- valued system design

ICCD Conversion Driven Design Flow EDA Tool Synthesize binary circuit from specification HDL specification Conversion Tool fast fully automated Convert to mixed radix component level design Flatten components to the gate level netlist Component library Place and route Final design AREA OF THE RESEARCH

ICCD …… mixerssplitters Conversion Basics …… binary inputs binary outputs binary …… quaternary inputs quaternary outputs quaternary Original binary datapath is given as a structural HDL netlist.Pairs of binary signals can be grouped into quaternary.Certain part of the circuit may remain binary.

ICCD Conversion Basics Signal converters:  A splitter converts one quaternary signal into two binary.  A mixer converts two binary signals into one quaternary.  The way the signals (gates) are grouped determines the efficiency of the conversion, therefore the conversion problem corresponds directly to the gate grouping problem.

ICCD Outline  Switching Balanced Codes  Conversion Driven Design Motivation Conversion Basics  Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results Conclusions Outline

ICCD Bitwise Gate Grouping A={A0, A1} B={B0, B1} Q = {Q0, Q1} Q = A·B Q0 = A0·B0 Q1 = A1·B1 A0A1 B0B1 Q0Q a bitwise quaternary component

ICCD Bitwise Gate Grouping Algorithm  Uses heuristics to extract bitwise meaning of signals from the flat netlist. Input and output port grouping is given Algorithm is iterative, based on breadth-first search Bitwise Regularity Ratio is used as an estimation criteria. It is calculated for each gate pair on each iteration. Bitwise Regularity Ratio (BRR) depends on how many quaternary links a pair of gates can form with respect to the state of the conversion on the given iteration.

ICCD Bitwise Gate Grouping Algorithm: Example BRR=2 original circuitconverted circuit * mixed radix components are shown as black boxes

ICCD Artificial Combinational Loops  Combinational loops can appear during the bitwise conversion while the original circuit is free of combinational loops.  Need special methodology to handle. Problems: If mixers wait for valid data from both inputs – deadlock. If mixers produce output regardless to spacers – invalid output. A signal should pass artificial combinational loop exactly 2 times before it produce a valid output.

ICCD Bitwise Gate Grouping Disadvantages of the algorithm:  Computational cost O(N) = 2N 2 log 2 2 N, N is a number of gates in the original circuit. Disadvantages of the approach:  Inefficient for circuits without bitwise nature of signals, e.g. S-boxes.  The algorithm can produce combinational loops. Bitwise (naive) approach is inefficient for CDD.

ICCD Outline  Switching Balanced Codes  Conversion Driven Design Motivation Conversion Basics  Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem  Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results Conclusions Outline

ICCD Operandwise Gate Grouping  Bitwise grouping is derived from the functional meaning of signals.  Operandwise grouping is derived from the structural positioning of gates – works with 2-input gates only. A0A1 B0B1 Q0Q A0B0 A1B1 Q0Q a bitwise quaternary componentan operandwise quaternary component A0 B0 A1 B1 Q0 Q1

ICCD Binary Trees Approach For binary tree structures within a netlist we can group inputs and outputs of gates to perform an operandwise grouping.

ICCD Binary Trees Approach Signals cannot be shared between groups, because it leads to duplication of gates. Gates with multiple fanout block operandwise grouping. – Remain binary

ICCD Quaternary-to-Binary Gates (Q/B Gates) Q/B gate – a gate with one quaternary input and one binary output.

ICCD Quaternary-to-Binary Gates (Q/B Gates)  A Q/B gate is a mixed radix component.  A Q/B gate is an incomplete operandwise group.  It can replace a splitter followed by a binary gate.

ICCD Operandwise Gate Grouping Algorithm  Phase I: group all signals regardless of gate fanouts (some gates will be duplicated).  Output ports can be grouped arbitrarily.  Phase II: analyse duplicates and discard groups leading to duplication.  Phase III: insert signal converters and Q/B gates. Computational cost of the algorithm is O(N) = 3N, where N is a number of gates in the original circuit.

ICCD Operandwise Gate Grouping Algorithm: Example original circuitconverted circuit Phase IPhase IIPhase III

ICCD Operandwise Gate Grouping Advantages of the algorithm:  Low computational cost.  It is highly modular: one can add more passes to the algorithm to increase efficiency of the conversion. Disadvantages of the algorithm:  Can produce significant “fractioning” of binary and quaternary parts of the circuit increasing the number of signal converters required.

ICCD Benchmark Results circuit dual-railmixed radix: dual-rail, 1-of-4 switching wires switching energyswitching wires switching energy averagestd. devaveragestd. dev 2-bit adder bit ripple carry adder bit multiplier* Kasumi S-box Kasumi S-box Kasumi S-box9* AES S-box* * original single-rail circuits were optimised in Synopsys.

ICCD Outline  Switching Balanced Codes  Conversion Driven Design Motivation Conversion Basics  Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem  Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results  Conclusions Outline

ICCD Conclusions  Conversion driven design technique was suggested in order to reuse popular EDA tools for MVL synthesis.  Binary and quaternary mixed radix was selected to improve the efficiency of the conversion.  Two conversion (gate grouping) algorithms were implemented and analysed. Bitwise approach is not efficient for CDD Operandwise approach is fast and flexible but not efficient enough in terms of saving switching energy. Future work:  Improve operandwise component implementations.  Add more heuristics to the operandwise algorithm to increase the efficiency of the conversion.

ICCD The End Thank you! Questions?