1. Automated Generation of Layout and Control for Quantum Circuits Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz University of California, Berkeley

2. Quantum applications Shor's algorithm  Exponential speedup in NP-hard factoring  Many computational blocks, over a million quantum gates Interesting Potential speedups  But: Automate design for large examples like this?

3. Why quantum CAD now? More and more quantum bits (qubits) realized DARPA Roadmap predicts 50 qubits by 2012  Ion traps: 30 qubits by 2008 Quantum circuit design done by hand so far However:  Complexity of layout and control  Verification of fault-tolerant properties  Automation (CAD) desirable Courtesy of Monroe group at U. Mich.

4. Electrode Control Qubits are atomic ions  Suspended in channels between electrodes Quantum gates performed by lasers  Only at certain trap locations Ions shuttled between laser sites to perform gates Classical control  Gate (laser) ops  Movement (electrode) ops Quantum Computing with Ion Traps Gate Location Qubit Ions Electrodes Courtesy of Chuang group, MIT

5. Ion Trap Physical Layout Input: Gate level quantum circuit  Bit lines  1-qubit gates  2-qubit gates Output:  Layout of channels  Gate locations  Initial locations of qubit ions  Movement/gate schedule  Control for schedule q0 q1 q2 q3 q4 q5 q6 q0 q3 q4 q5 q6 q1 q2 Qubits Time

6. Wire channels will be large  10s of microns wide Gate sites equally large  Also requires laser routing One layer of traps (no “metal{1,2,3...}”)  All planar routing Reuse wire and gate resources Ion Trap Technology Constraints Courtesy of Chuang group, MIT

7. Physical Layout Flow

8. Scheduling Quantum Circuits Goal: Schedule given circuit on given layout Gates fire with inputs Look for best gate site Prioritize critical gates Feedback if cannot schedule

9. Scheduling Demo a0 a1a2 a3a4 a5 Movement/gate Scheduler Time 0: move a0: block 2,4,6,5 Time 14: gate laser: block 5 Time 114: move a0: block 6,2,3 Time 120: move a3: block 6,7 Time 125: gate laser: block 6 Time 130: gate laser: block 3 Time 225: move a0: block 2,1 Time 230: move a3: block 6,8 Time 231: gate laser: block 1 Time 236: gate laser: block 8 Time 331: move a0: block 2,0 Time 336: move a3: block 6,5

10. Scheduler Control Control Laser Control Measurement Control High-level Control Time 0:move q0: block 1,2 Time 6: gate laser: block 2 Schedule control synthesis

11. Physical Layout Flow

12. P&R Heuristic: Greedy Places minimal gates Places layout incrementally  Uses scheduler feedback Empty layout passed to scheduler Scheduler feedback to P&R  2 qubits needed for gate P&R adds gate and channel resources Re-schedule

13. P&R Heuristic: Collapsed Dataflow Gate locations placed in dataflow order  Qubits flow left to right  Initial dataflow geometry folded and sorted  Channels routed to reflect dataflow edges Too many gate locations, collapse dataflow  Using scheduler feedback, identify latency critical edges  Merge critical node pairs  Reroute channels q0 q1 q2 q3 q0 q1 q2 q3 q0 q1 q2 q3

14. Experiments Evaluate generated layouts  Area: final rectangular area  Latency: time to implement movement/gate schedule Benchmarks  Quantum error correction/encoding circuits CircuitGatesQubits CSS 7-bit encoder217 Golay 23-bit encoder11623 CSS 7-bit error correct13621 CSS concatenated encoder24549

15. Results: Golay 23-qubit encode Greedy P&R Collapsed Dataflow P&R 168 block bounding box area 2457 microsecond latency Good area, few channels 713 block bounding box area 2264 microsecond latency Pipelinable

16. Results: CSS concatenated encoder Greedy P&R 936 block bounding box area 4791 microsecond latency Greedy breaks down 1617 block bounding box area 1828 microsecond latency More scalable with lots of gates Collapsed Dataflow P&R

17. Quantum Circuit CAD: Future Work Working on full CAD flow for quantum circuit design  Started with physical layout Better heuristics for layout  Leverage ideas from classical CAD Interoperability with 3 rd party tools  QuiDDPro, Malignant, CHP  Encourage other research into tools to plug into this flow

18. Conclusion Scheduling heuristic for ion trap quantum circuits  Sequences gate and communication ops on arbitrary layout  Synthesizes classical control HDL Iterative place and route heuristics  Simple greedy minimizes gate sites (lasers)  Collapsed dataflow more scalable and potentially good throughput First steps toward larger CAD flow for quantum computing  Provide tools for experimentalists as more qubits implemented  Testbed for new circuit designs for fault tolerance, new algorithms

19. Questions?

21. Future Work Add hierarchical P&R for larger circuits Fault tolerance layout evaluation metric Automatic insertion of error correction circuits Automatic selection of error correcting codes

22. Ion Trap Control Ion trap QC is coordinated ballistic ion movement and laser operation Ballistic corner turn takes 120 clock cycles, many electrodes Significant control problem Movement and gates explicitly controlled already  Use it to multiplex over gates and channels

23. Fault Tolerant Circuit Synthesis Simple logical circuits are complex at the physical level FT gates and correction can be automated

24. Scheduling II Extract dataflow graph from circuit Gates fire as soon as input qubits are ready Gate performed at closest gate site to inputs

25. Quantum Circuits At-a-glance Qubit = discrete 2-level quantum system Circuit model has reversible gates No wire fanout (no-cloning) Qubits are superposition of “0” and “1”  Exponential algorithmic speedup relies on superposition Superposition fragile, needs a lot of fault tolerance  Current gate failure rates around 1% To read out data, must measure qubit

26. Grid Flow Ion Trap Physical Layout Qubit Placement Quantum Program Description Scheduling Operations Classical Control Pattern

27. Better CAD Flow Fault Tolerance Transformations Ion Trap Physical Layout Qubit Placement Scheduling Operations Classical Control Quantum Program

28. Grid P&R Problems Scheduled qubit paths are inefficient Gate usage inefficient, wasted space Exponential search spaces of layout tiles, qubit positions, grid size Knowledge of circuit topology should be used for layout Develop two heuristics for placement and routing

29. Prior Work: Grid Layouts Good grid tiling Bad grid tiling  4x performance difference!

30. Varying Grid Structures We evaluated performance of alternate grid structures 1. Pick tile configuration 2. Create full layout 3. Assign qubit locations 4. Schedule operations

31. Prior work in layout used regular grid of channels/gate sites Program dictates grid size, not structure Assign qubit starting positions, let scheduler do rest Prior Work – Grid Layouts x y

32. Results: CSS 7-qubit encode Greedy P&R Dataflow P&R 36 block bounding box area 648 microsecond latency Pretty good latency Minimal congestion 126 block bounding box area 795 microsecond latency No latency improvement

33. Quantum Layout Flow Automate gate placement/routing, scheduling Ion Trap Place & Route Schedule moves & gates Classical Control Synthesis Quantum Circuit Netlist Classical Control Synthesis

34. Quantum Layout Flow Automate gate placement/routing, scheduling Ion Trap Place & Route Schedule moves & gates Classical Control Synthesis Quantum Circuit Netlist Schedule moves & gates

35. Quantum Layout Flow Automate gate placement/routing, scheduling Ion Trap Place & Route Schedule moves & gates Classical Control Synthesis Quantum Circuit Netlist Ion Trap Place & Route Developed two P&R heuristics  Greedy  Collapsed dataflow

36. q0 q1 q2 q3 q0 q1 q2 q3

37. P&R Heuristic: Grouped Dataflow Multiple gates can be tied to single gate location to minimize communication Critical paths through dataflow graph are shortened by mapping multiple gates to single location