1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

2 Workshop 6 – Data Types B Arrays Memory Modeling Parameters Exercise 6

3 Arrays Arrays are allowed for reg, integer, time and vector register data types. Multi-dimensional arrays can also be declared with any number of dimensions. Arrays of nets can also be used to connect ports of generated instances. Definition syntax {size} {array_size} (reg [N:0], integer, time) [0 : M] Reference syntax {array_reference} {bit_reference}

4 Array Examples reg [7:0] my_reg [0:31] ; // Array of 32 byte-wide registers integer matrix [4:0] [0:255] ; // 2-dimentional Array of integers time chk_point [1:100] ; // 100 time checkpoint variables Array my_reg[15] ; // Referencing the 16th byte of the array register integer [3:0] out [31:0] ; // 32 4-bits output elements out[27][3] ; // Referencing bit number 3 in element number 27

5 Bit and part selects within arrays Part select within array: reg [31:0] Data_RAM[0:255] ; output reg [7:0] data_out1 ; output reg [15:0] data_out2 ; Exercise: Write expressions to: 1. Read 2nd byte from address 11 to data_out1. 2. Read 2nd and 3rd bytes from address 77 to data_out2. Answers: 1. data_out1 = Data_RAM[11][15:8] ; 2. data_out2 = Data_RAM[77][23:8] ; ● Verilog allows bit selects and part selects of array words, to be directly accessed. Example: Select the high-order byte of one word in a 2-dimensional array of 32-bit reg variables reg [31:0] array2 [0:255][0:15] ; wire [7:0] out2 = array2[100][7][31:24] ;

6 Memory Modeling In digital simulation one needs to model: - Register Files - RAMs - ROMs - FIFOs - CPU Stack and Caches Memories are modeled as array of registers. reg [7:0] my_memory[0:1023] ; // 1K bytes memory // read a byte from address 511 data_out <= my_memory[511] ; // Write a byte to address 374 my_memory[374] <= data_in ;

7 Parameters Parameter: A constant value declared within a module structure with the keyword “parameter”. The value can be used to define a set of attributes for the module which can characterize its behavior as well as its physical representation. Parameters allow us to define generic module. Hardcoded numbers should be avoided in module definition. Parameter values for each module instance can be overridden individually at compilation time. This allows module instances to be customized. Parameters values can be changed at module instantiation or by using the defparam statement. localparam keyword provides protection against defparam unintentional modifications.

8 Parameters tips defparam could be applied on parameter in any hierarchy in design: defparam top.sram_ctrl.wr_cmd.dt_width = 32 ; Parameters can get the result of operation on other parameters: parameter a = 8 ; parameter b = 4 ; parameter c = a * b ; // c = 8 x 4 = 32

9 Parameters tips - continue Parameters defined as the result of operation on other parameters: // module FIFO_24bx16 parameter data_width = 24 ; // 24 bits words parameter log2_depth = 4 ; // # of rd/wr pointers bits // FIFO depth = 2** log2_depth = 16 parameter max_count = 2** log 2_ depth ; reg [data_width-1 : 0] fifo[0 : max_count -1] ; reg [log2_depth : 0] depth_cnt ; // for full/empty flags reg [log2_depth-1 : 0] rd_ptr, wr_ptr ; // rd/wr pointers

10 Parameter syntax To define parameter: parameter (or localparam) = ; To override the value of defined parameter: defparam. = ; Instantiate modules with new parameter values:  Assignment by ordered list # (value 1, 2, ….n) () ; Note: if there is a missing value, last one gets the default value  Assignment by name # (.a(value),…,.n(value)) () ; Note: if there is a missing name, it gets the default value

11 Parameters Examples parameter width = 32 ; wire [width-1:0] din ; // Data input width definition localparam state1 = 4’b0001, /* state machine encoding state2 = 4’b0010, cannot be changed */ state3 = 4’b0100, state4 = 4’b1000 ; module hello_world ; parameter id_num = 0 ; // define module id number = 0 …… module top ; defparam w1.id_num = 1, w2.id_num = 2 ; // instantiate two hello_world modules hello_world w1 () ; hello_world w2 () ; endmodule

12 Parameters Examples cont. module bus_master ; parameter delay1 = 2 ; // rise time parameter delay2 = 3 ;// fall time parameter delay3 = 7 ;// turn-off time endmodule Top-level module passes parameters to instances b1, b2, b3 Assignment by order list: bus_master # (4, 5, 6) b1 () ; // b1: delay1=4, delay2=5, delay3=6 bus_master # (9, 4) b2 () ; // b2: delay1=9, delay2=4, delay3=7 Assignment by name: bus_master # (.delay2(4), delay3(7)) b3 () ; // b3: delay1=2, delay2=4, delay3=7

13 Exercise 6 Data Memory. Asynchronous read, synchronous write SRAM. Initialized by data_RAM.txt file. Fibonacci Series Generator. Output the 1 st 16 elements. Fibonacci Series Generator, utilizing Dual Port Register File.