Introduction of Intel Processors

Intel 4004 (First Microprocessor) : 1969 Revolution from fixed functionality to variable Handled 4 bit data Had 46 instructions Allowed 4KB of program code and 1KB of data.

Intel 8-bit processors They are 8008, 8080 and 8085 They were used in many early microcomputers in applications such as electronic instruments and printers

Intel 16-bit processors They included 8086, 8088 and 80286

Intel 32-bit processors They include 80386 and 80486. First they introduced 80386DX, 80386SX and 80386SL. It was compatible with 8088/8086/80286 80386DX(DX refers to floating point capability) 80386SX(SX refers to 16-bit data bus) It offers 24 bit address bus(16MB physical m/m) 80386SL(offered several power management options and sleep modes to conserve battery power for laptops)

Intel 32-bit processor - 80486 80486DX – Improved with memory cache and math coprocessor 80486SX – Does not have math coprocessor Clock doubler/tribler were also released (75% faster than the comparable non-doubled processor) DX2-66  33MHz DX2-50  25MHz DX4-100  25MHz DX4-75  25MHz

80386DX

Features of 80386DX It supports 8/16/32 bit data operands It has 32-bit internal registers It supports 32-bit data bus and 32-bit non-multiplexed address bus It supports Physical Address of 4GB Virtual Address of 64TB Maximum Segment size of 4GB

Features of 80386DX It operates in 3 different modes Real Protected Virtual 8086 MMU provides virtual memory, paging and 4 levels of protection Clock Frequency : 20,25 and 33MHz It has 132 pin package

Architecture of 80386 UQ: Draw the block diagram of the 80386 DX Processor and explain each block in brief

Architecture of 80386 Three Sections: Bus Interface units Central Processing Unit Memory Management Unit

Architecture of 80386 The internal architecture of 80386 is divided into three sections: Central Processing Unit Memory Management Unit Bus Interface unit

Central Processing Unit

Central Processing Unit The CPU is further divided into: Instruction Unit Execution Unit Instruction Unit: It decodes the opcode bytes received from the 16-byte instruction queue and arranges them into a 3-decoded instruction queue. After decoding it is passed to control section for deriving necessary control signals

Central Processing Unit Execution Unit: It has 8 general purpose and 8 special purpose registers which either handles data or addresses The 64-bit barrel shifter increases the speed of all shift, rotate, multiply and divide operations The multiply/divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time(Even 32bit multiplication is done in 1µs)

Central Processing Unit Element of the EU Arithmetic/logic unit (ALU) Performs the operation identified by ADD, SUB, AND, etc. Flags register Holds status and control information General-purpose registers Holds address or data information Control ROM Contains microcode sequences that define operations performed by machine instructions Special multiply, shift, and barrel shift hardware Accelerate multiply, divide, and rotate operations

Memory Management Unit

Memory Management Unit MMU consists of a segmentation unit and paging unit Segmentation Unit: It allows the use of two address components - segment and offset – for relocability and sharing of data It allows a maximum segment size of 4GB It provides a 4-level protection mechanism for protecting and isolating system’s code and data from those of application program

Memory Management Unit The limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in memory segment. Paging Unit It organizes physical memory in terms of pages of 4KB size It works under the control of segmentation unit It converts linear addresses into physical addresses The control and attribute PLA checks privileges at page level.

Bus Interface Unit It has a prioritizer to resolve the priority of various bus requests. This controls the access of the bus The address driver drives the bus enable and address signals A2 – A31. The pipeline/bus size unit handles the control signals for pipelining and dynamic bus sizing units

Bus Interface Unit The data buffers interface the internal data bus with system bus

NEXT : Signal Interface of 80386DX