A Novel 2.4 GHz CMOS Class-E Power Amplifier with Efficient Power Control for Wireless Communications R. Meshkin, A. Saberkari*, and M. Niaboli Department of Electrical Engineering University of Guilan Rasht, Iran International Conference on Electronics, Circuits and Systems Athens, Greece Dec. 2010

Outline Introduction Baseline Class-E Power Amplifier Topology Expressions and Relationships Conventional Power Control Techniques Design Procedure Circuit Characterization Conclusion 2 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Introduction Power Amplifier (PA) The Last Building Block of a Transmitter Chain in Transceiver ICs The Most Power Consuming Block in any RF Transmitter Linear and Nonlinear PAs Linearity is in conflict with Efficiency. Constant Envelope Modulation Scheme => Nonlinear PAs Class-E PA => Better Choice in Terms of Circuit Simplicity High Efficiency Good Performance at Higher Frequencies 3 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion Conclusion

Classical Class-E Power Amplifier Topology Baseline Class-E PA Topology Soft Switching Properties: Classical Class-E Power Amplifier Topology 4 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Expressions and Relationships Load Network Components Value: Ropt = Optimum Load Resistance Pout = Desired Output Power ω = Resonant Frequency Vdd = Supply Voltage Efficiency: Pdc = Supply Power Pout = Output Power Pin = Input Power 5 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Conventional Power Control Techniques Power Control with Variable Supply Voltage 6 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Conventional Power Control Techniques Power Control with Parallel Amplification 7 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Conventional Power Control Techniques Power Control with Array of Switches with Different Sizes 8 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Proposed Class-E Power Amplifier Design Procedure Two-Stage Configuration (Driver Stage and Power Stage) Cascode Transistor: High Isolation from the Input to the Output Protect Switching Transistors (Breakdown) Class-E Driver Stage => More Efficiency & Closer to Optimum Driving Signal Matching Network => As Much as Possible Power from Source to the Load Proposed Class-E Power Amplifier 9 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Proposed Structure for Output Power Control Design Procedure Output Power Control: Changing the Size of the Switching Devices, And Suitable External Shunt Capacitors Calculated for Each Steps of Output Power Small Size Controlling Switches => located in the Gate Terminal due to the Low Current of Gate Proposed Structure for Output Power Control 10 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Circuit Elements Value Design Procedure Circuit Elements Value 0.71 nH Lf M1,M2 1.39 nH L1 M3,M4 1.1 nH L2 M3΄,M4΄ 50 Ω RL M3΄΄,M4΄΄ 0.2 V Vbias1 M3΄΄΄,M4΄΄΄ 0.65 V Vbias2 M3΄΄΄΄,M4΄΄΄΄ 1.8 V Vdd 2.3 pF Cm1 52 fF CP 1.55 nH Lm1 890 fF CP΄ 10 pF Cm2 953 fF CP΄΄ 0.6 nH Lm2 990 fF CP΄΄΄ 2.8 pF Cm3 1 pF CP΄΄΄΄ 1.28 nH Lm3 5 pF Cf 11 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Design Procedure Chip Layout 1381 µm*1234 µm 12 Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Drain Current and Voltage Waveforms of Cascode Transistor M4 Circuit Characterization Drain Current and Voltage Waveforms of Cascode Transistor M4 13 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Output Power and PAE Versus Supply Voltage Circuit Characterization Output Power and PAE Versus Supply Voltage 14 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Output Power and PAE as a Function of Frequency Circuit Characterization Output Power and PAE as a Function of Frequency 15 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Circuit Characterization Output spectrum 16 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

PAE Values for Each Output Power Step Circuit Characterization PAE Values for Each Output Power Step PAE (%) Output Power (dBm) Control Word 57 21.09 10000 47.5 20 01000 41 19 00100 36 18 00010 33 17 00001 17 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Performances in Comparison with Previous Works Circuit Characterization Performances in Comparison with Previous Works PAE (%) Output Power (dBm) Supply (V) Frequency (GHz) Technology (µm) References 48 24 2.5 2.4 CMOS 0.25 [1] 58 31 1.7 CMOS 0.13 [2] 38.8 25.8 7 [3] 27.8 19.2 3.3 CMOS 0.18 [4] 57 21.09 1.8 This work [1] V. R. Vathulya, T. Sowlati and D. Leenaerts, 2001. [2] R. Brama, L. Larcher, A. Mazzanti and F. Svelto, 2007. [3] H. Fouad, A.H. Zekry and K. Fawzy, 2009. [4] S.A.Z, Murad, R.K. Pokharel, H. Kanaya and K. Yoshida, 2010. 18 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Comparison of PAE Drop in Different Output power Control Method Circuit Characterization Comparison of PAE Drop in Different Output power Control Method Drop (%) Control Method References 22% Parallel Amplification [1] 15% Change Driver Stage Size [2] 10% Bias Regulation [3] 14.5% Proposed Technique This work [1] A. Sirvani, D. K. Su, B. A. Wooley, 2002. [2] M. M. Hella and M. Ismail, 2002. [3] C. Wei, L.Wei and H. Shizhen, 2009. 19 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion

Conclusion Reviewed Concepts of Classical Class-E Power Amplifiers Presented Topological Modifications that Improve PAE and Circuit Integration Capability Presented New Efficiently Output Power Control Technique Based on the Array of Switches and Capacitors 20 Introduction Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize Conclusion