1. A 2.4-GHz 0.18-um CMOS Self-Biased Cascode Power Amplifier
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003
A 2.4-GHz 0.18-um CMOS Self-Biased Cascode Power Amplifier
Tirdad Sowlati, Member, IEEE, and Domine M. W. Leenaerts, Senior Member, IEEE
指導老師:林志明
學生:黃政德
系級:積體所研一

2. Introduction (1)
Oxide breakdown sets a limit on the maximum signal swing on drain.
Hot carrier degradation is a reliability issue. It increases the threshold voltage and consequently degrades the performance of the device.
Cascode configuration and thick-oxide transistors have been used.

3. Introduction (2)
This work demonstrates a 0.18-um CMOS self-biased cascode RF power amplifier that operates at 2.4 GHz and provides 23 dBm from a 2.4-V supply voltage for Class-1 Bluetooth application.
By using standard oxide thickness devices in the process, the design takes full advantage of the technology and its high Ft.

4. Conventional cascode amplifier and Voltage waveforms versus time

5. Self-biased cascode amplifier and Voltage waveforms versus time

6. Bootstrapped cascode amplifier and Voltage waveforms versus time

7. Two-stage self-biased cascode PA

8. Simulate output power, gain, and PAE

9. Conventional and Self-biased Cascode PA

10. Microphotograph of the PA

11. Measured Pout , gain, and PAE versus Pin

12. Pout versus time of continuous operation

13. Bluetooth spectrum at the output of the PA

14. SLIDING BIAS TECHNIQUE
To improve the linearity of a PA:
Operate the PA in class A/AB mode
Use a bias boosting or gain boosting at the compression point
Employ a de-biasing technique at low and intermediate power levels to have the same gain at the maximum power

15. Measured Gain and PAE versus Pout for constant/sliding gate bias voltages

16. Measured phase variations versus inputs power for constant/sliding bias

17. Conclusion
A self-biased cascode topology was applied to reduce hot carrier effects.
No performance degradation occurs after ten days of continuous operation under maximum output power conditions.
Using a sliding biasing technique on both stages, improve the PAE at low/mid-power level and linearize the PA.