1 Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments Federico Faccio for the CERN(PH/MIC)-DACEL * collaboration * DACEL is an INFN project involving the INFN sections of Bari, Bergamo, Bologna, Firenze, Padova, Pavia and Torino

VI FEE Meeting Perugia, May 2006 F.Faccio2 Outline Past, present and future: 250nm CMOS with HBD approach for the LHC experiments Motivation for moving to 130nm CMOS Irradiation results (TID) for 3 different manufacturers (Foundries) SEE results Conclusion

VI FEE Meeting Perugia, May 2006 F.Faccio3 TID effects in CMOS technologies (1) Bird’s beak Field oxide Parasitic MOS Parasitic channel Source Drain 1. Effects in the thin gate oxide 2. Effects in the thick lateral isolation oxide (STI) between source and drain of a transistor

VI FEE Meeting Perugia, May 2006 F.Faccio4 TID effects in CMOS technologies (2) 3. Effects in the isolation oxide (STI), in between n-well or diffusions

VI FEE Meeting Perugia, May 2006 F.Faccio Past and present: 250nm CMOS S D G Hardness By Design (HBD) approach has been used: ELT transistors

VI FEE Meeting Perugia, May 2006 F.Faccio Past and present: 250nm CMOS S D G p+ guardring Hardness By Design (HBD) approach has been used: guardrings N+ DRAINN+ SOURCE OXIDE SUBSTRATE V DD SS V P+ GUARD SS V

VI FEE Meeting Perugia, May 2006 F.Faccio7 HEP Foundry Service in 250nm CMOS MPW service organized for more than 100 different ASICs More than 20 different designs in production (some are multi- ASIC) More than 2000 wafers (8-inch) produced!

VI FEE Meeting Perugia, May 2006 F.Faccio8 Motivation to move to 130nm LHC upgrades & SLHC will require higher- performance ICs, tolerant to larger TID levels 250nm is already an old process and will not stay around much longer More-modern CMOS processes have the potential of higher TID tolerance and much better performance What is the radiation tolerance? HBD needed?

VI FEE Meeting Perugia, May 2006 F.Faccio9 Outline Past, present and future Irradiation results (TID) for 3 different manufacturers (Foundries) Experimental details Core transistors, linear layout Core transistors, ELT I/O transistors Need for guardrings… SEE results Conclusion

VI FEE Meeting Perugia, May 2006 F.Faccio10 Test structures and measurement setup 3 commercial 130nm CMOS processes: foundries A,B and C Some are PMDs from foundry, some custom-designed test ICs NMOS and PMOS transistors, core and I/O devices (different oxide thickness), FOXFETs Testing done at probe station – no bonding required Irradiation with X-rays at CERN up to Mrad, under worst case static bias Further studies (p source, reliability, SEGR, noise, …) are under way

VI FEE Meeting Perugia, May 2006 F.Faccio11 Core NMOS transistors, linear layout (1) Wide transistors (W > 1  m): When the transistor is off or in the weak inversion regime: Leakage current appears (for all transistor sizes) Weak inversion curve is distorted Foundry A, 2/0.12 Narrow transistors (W < 0.8  m): An apparent Vth shift (decrease) for narrow channel transistors The narrower the transistor, the larger the Vth shift (RINCE) Foundry A, 0.16/0.12

VI FEE Meeting Perugia, May 2006 F.Faccio12 annealing pre-rad Core NMOS transistors, linear layout (2) Foundry C Foundry A Effect on the leakage current Peak in leakage at a TID of 1-5Mrad Peaking dependent on dose rate and temperature, difficult to estimate in real environment Foundry B

VI FEE Meeting Perugia, May 2006 F.Faccio13 Core NMOS transistors, linear layout (3) Effect on the threshold voltage Peak in Vth shift at a TID of 1- 5Mrad (A and C) The narrower the transistor, the larger the Vth shift (RINCE) Peaking dependent on dose rate and temperature, difficult to estimate in real environment Foundry C Foundry A Foundry B

VI FEE Meeting Perugia, May 2006 F.Faccio14 Radiation-induced edge effects - NMOS STI Depletion region Polysilicongate E field lines - - STI Depletion region Polysilicongate E field lines Oxide trapped charge Interface states V GS IDID 0 Main transistor Lateral parasitic transistor

VI FEE Meeting Perugia, May 2006 F.Faccio15 Core PMOS transistors, linear layout (1) No change in the weak inversion regime, no leakage An apparent Vth shift (decrease) for narrow channel transistors The narrower the transistor, the larger the Vth shift Foundry C, 0.28/0.12Foundry B, 0.14/0.13 Foundry A, 0.16/0.12

VI FEE Meeting Perugia, May 2006 F.Faccio16 Radiation-induced edge effects - PMOS STI Depletion region Polysilicongate E field lines - - STI Depletion region Polysilicongate E field lines Oxide trapped charge Interface states V GS IDID 0 Main transistor Lateral parasitic transistor

VI FEE Meeting Perugia, May 2006 F.Faccio17 Core NMOS transistors, enclosed layout (ELT) The radiation hardness of the gate oxide is such that practically no effect is observed – verified for 2 foundries (A up to 140Mrad, B up to 30Mrad) Example: Foundry A

VI FEE Meeting Perugia, May 2006 F.Faccio18 I/O transistors, linear layout Large effect for all sizes, but more important for narrow channel transistors Results different with Foundry, but for all enclosed layout is required already for TID levels of the order of krad (NMOS) Effect is not negligible also for ELTs: relevant Vth shift! Foundry A, NMOS 0.36/0.24 Foundry A, PMOS 2/0.24

VI FEE Meeting Perugia, May 2006 F.Faccio19 Are guardrings systematically needed? (1) FoxFETs are “Field Oxide Transistors” Good to characterize isolation properties with TID Structures available in only 1 technology (1 only Foundry) 1. N+diffusion to N+diffusion (source/drain of two neighbor NMOS transistors)

VI FEE Meeting Perugia, May 2006 F.Faccio20 Are guardrings systematically needed? (2) 2. N+diffusion to Nwell (Nwell with PMOS logic to drain/source of NMOS logic) SUBSTRATE N+ diffusion STI OXIDE S N+ WELL CONTACT N WELL D Metal 1 G STI oxide SUBSTRATE STI OXIDE S S N+ WELL CONTACT N WELL D N+ WELL CONTACT N WELL D Metal 1 G STI oxide Vg=2.5V

VI FEE Meeting Perugia, May 2006 F.Faccio21 Without guardringPartial guardringFull guardring Are guardrings systematically needed? (3) Vdd N-well Vdd N-well Realistic test structure with series of Inverters + DFF along 350um, and with different separation between n-well (PMOS logic) and NMOS:

VI FEE Meeting Perugia, May 2006 F.Faccio22 Are guardrings systematically needed? (4)

VI FEE Meeting Perugia, May 2006 F.Faccio23 Outline Past, present and future Irradiation results (TID) for 3 different manufacturers (Foundries) SEE results Conclusion

VI FEE Meeting Perugia, May 2006 F.Faccio24 SEE results: the SRAM circuit 16kbit SRAM test circuit designed using the SRAM generator from a commercial library provider – not dedicated rad-tolerant design! Test performed with Heavy Ions at the Legnaro National Laboratories accelerator in June 2005

VI FEE Meeting Perugia, May 2006 F.Faccio25 Heavy Ion irradiation results Test at Vdd=1.5 and 1.25 V, results very similar Sensitivity to very low LET values (threshold below 1.6 MeV/cm 2 mg) Comparison with 0.25  m memory (rad-tol design!!): Cross-section times larger in LHC environment

VI FEE Meeting Perugia, May 2006 F.Faccio26 Challenges for 130nm Technology more expensive than ¼ micron: Strong push for first working silicon Strong push for common solutions to similar problems Technology more complex than ¼ micron: Reduced Vdd, difficult for analog Physical effects can not be ignored: proximity effects, filling requirements, “cheesing”, … As a consequence, design rules are considerably more complex (impressive growth of the design manual) Larger number of tools is needed Competence in radiation effects are also required If non-enclosed transistors are used To protect circuits from SEEs All competences in technology, design techniques and tools necessary for a successful project are more difficult to gather in a group of small size

VI FEE Meeting Perugia, May 2006 F.Faccio27 Conclusion HBD in quarter micron has made LHC electronics possible/affordable: large scale application of HBD is a reality! Natural radiation tolerance of 130nm better than for the quarter micron technology (not for I/O transistors), but Mrad-level still requires HBD for reliable tolerance Large effort required to develop library, acquire tools, master the technology: Working with 130nm is MUCH more complex and expensive; pressure to get quickly to working silicon CERN is preparing a frame contract with 1 selected Foundry, to develop library/design kit/design flow serving the whole HEP community