Radiation effects in deep submicron CMOS technologies Federico Faccio 1.

Radiation effects in deep submicron CMOS technologies Federico Faccio 1

Outline Radiation effects in CMOS technologies Influence of scaling Hardness-By-Design (HBD) Results in the 130nm generation Results in the 90nm generation A quick look beyond 90nm ESE seminar, Jan2010 F.Faccio2

Interaction of photons and particles with matter Radiation effects are traceable to the interaction of radiation (photons, particles) with the materials composing the electronics (mainly Si and SiO 2 in modern ICs). Energy can be released by the photon/particle via ionization or non- ionization mechanisms ESE seminar, Jan2010 F.Faccio3Neutronn e he h e he he h e h e h p n i nhadronsn p Si Dislocation of atoms from lattice Heavy Ion eh eh eh eh eh eh eh eh eh eh eh eh eh eh h h h e e e e e e e e h h h h h h h h h h h h h h e e e e e e e ee h ehhh hh e ee e e e ee hhhh hh iProtoneh eh eh eh eh eh p e he h e he he h e h e h p ni p Small density of e- h pairs Large density of e- h pairs Small (proton) or no (neutron) density for direct ionization. Possible high density from Heavy Ion produced from nuclear interaction of the particle with Silicon nucleus. Photon (X,  ) eh Silicon Nuclear interaction

Radiation effect from the interaction Very simplified summary ParticlesRadiation effect Ionizing energy loss Small charge densityAll (photons, electrons, charged hadrons, Heavy Ions, …) Total Ionizing Dose (TID) Large charge densityHeavy Ions (maybe from hadron nuclear interaction in Si) Single Event Effects Non ionizing energy loss Hadrons (neutrons, protons, ….) Displacement damage ESE seminar, Jan2010F.Faccio4

Radiation effects in CMOS technologies ESE seminar, Jan2010 F.Faccio5 Cumulative effects Single Event Effects (SEE) Total Ionizing Dose (TID) Permanent SEEs SEL SEGR ? Static SEEs SEU, SEFI Digital ICs Transient SEEs Combinational logic Operational amplifiers Any influence? Reliability Any influence?

TID effects in CMOS technologies (1) ESE seminar, Jan2010 F.Faccio6 Bird’s beak Field oxide Parasitic MOS Parasitic channel Source Drain 1. Effects in the thin gate oxide 2. Effects in the thick lateral isolation oxide (STI) between source and drain of a transistor

ESE seminar, Jan2010 F.Faccio7 TID effects in CMOS technologies (2) 3. Effects in the isolation oxide (STI), in between n-well or diffusions

TID-induced failure Increase in leakage current affects static power consumption, until device failure occurs ESE seminar, Jan2010 F.Faccio8

Single Event Effects SEEs occur when the charge deposition from the individual interaction of a particle is sufficient to disrupt the functionality of the hit circuit (temporarily or permanently) Any particle has a given probability to originate an SEE – stochastic nature Sensitivity of an IC to SEEs is characterized by a cross-section curve which expresses the probability for the event to occur in a given radiation environment ESE seminar, Jan2010 F.Faccio9

Single Event Upset (SEU) (1) ESE seminar, Jan2010 F.Faccio10 The e-h pairs created by an ionizing particle can be collected by a junction that is part of a circuit where a logic level is stored (logic 0 or 1). This can induce the “flip” of the logic level stored. This event is called an “upset” or a “soft error”. This typically happens in memories and registers. The following example is for an SRAM cell. GND V DD Node stroke by the particle p- substrate Striking particle Depletion region: e-h pairs are collected by n+ drain and substrate => those collected by the drain can contribute to SEU n+ drain e-h pairs in this region recombine immediately (lots of free electrons available in this n+ region) High density of e-h pairs in this region can instantaneusly change effective doping in this low-doped region, and modify electric fields. This is called “funneling”. Charge can hence be collected from this region to the n+ drain, although a portion of it will arrive “too late” to contribute to SEU

Single Event Upset (SEU) (2) ESE seminar, Jan2010 F.Faccio11 GND V DD 1. Initial condition (correct value stored) 0 1 Charge collected at the drain of NMOS T1 tends to lower the potential of the node B to gnd. PMOS T2 provides current from Vdd to compensate, but has a limited current capability. If the collected charge is large enough, the voltage of node B drops below Vdd/2 T1 T2 Node B Node A GND V DD 2. Final condition (wrong value stored) 1 0 When node B drops below Vdd/2, the other inverter in the SRAM cell changes its output (node A) to logic 1. This opens T2 and closes T1, latching the wrong data in the memory cell. T1 T2 Node B Node A

“Digital” Single Event Transient (SET) Particle hit in combinatorial logic: with modern fast technologies, the induced pulse can propagate through the logic until it is possibly latched in a register Latching probability proportional to clock frequency Linear behaviour with clock frequency is observed ESE seminar, Jan2010F.Faccio12 SET SEU Total Error = SET + SEU Errors Frequency Register Combinatorial logic

Permanent/Destructive SEEs (Hard errors) ESE seminar, Jan2010 F.Faccio13 SEGR=> Single Event Gate Rupture Typical in power devices. Could-it be triggered also in low-voltage devices – maybe due to the accumulation of TID changing the natural sensitivity of the device to SEGR? SEL=> Single Event Latchup Beyond the modes normally addressed by the manufacturer (I/Os), latchup can be initiated by ionizing particles (SEL) in any place of the circuit Beyond the modes normally addressed by the manufacturer (I/Os), latchup can be initiated by ionizing particles (SEL) in any place of the circuit n well p substrate V DD contact p + R1 R2 R3 R4 R5 R6 V DD source V SS source V SS contact p + n +

CMOS technology scaling ESE seminar, Jan2010 F.Faccio15

Radiation effects and t ox scaling ESE seminar, Jan2010 F.Faccio16 N.S. Saks et al., IEEE TNS, Dec. 1984 and Dec. 1986 Damage decreases with gate oxide thickness Oxide trapped chargeInterface states

Tendency confirmed Gate oxides in commercial CMOS technologies did follow the curve drawn by Saks and co-workers! ESE seminar, Jan2010F.Faccio17 Technology node (  m)

SEU and scaling ESE seminar, Jan2010 F.Faccio18 The reduction in voltage supply and node capacitance decreases the threshold charge for SEU. This seems to indicate that SEU sensitivity gets larger with down-scaling. Survey of sensitivity of different commercial products in time does not completely agree with that: All sources agree: DRAM sensitivity has been scaling down (cell area scaling has outpaced the decrease in stored charge). Picture somewhat less clear for SRAMs P.Hazuka et al (work funded by Intel) developed a model to predict SER scaling with Lg. The results suggest that the per-bit sensitivity decreases –at least- linearly with Lg Overall: FIT/MB decreases, but FIT/chip increases Not only Vdd and node capacitance have to be taken into account: sensitive area and charge collection efficiency are also important and change with technology generation!

SEL and scaling Retrograde wells Trench isolation V DD reduced ESE seminar, Jan2010 F.Faccio19 All these issues help in preventing SEL, but they might not be always effective n well p substrate V DD contact p + R1 R2 R3 R4 R5 R6 V DD source V SS source V SS contact p + n + decrease

Hardness by Design (HBD) ESE seminar, Jan2010 F.Faccio S D G ELT transistors efficiently prevent source-drain leakage currents

Hardness by Design (HBD) ESE seminar, Jan2010 F.Faccio S D G p+ guardring Guardrings efficiently prevent leakage between n+ diffusions and wells (and contribute to decreasing SEL sensitivity as well) N+ DRAINN+ SOURCE OXIDE SUBSTRATE V DD SS V P+ GUARD SS V + + + ++ + + + + + +

Use of HBD in 250nm CMOS LHC ASICs have largely made use of HBD in a commercial quarter micron process MPW service organized for more than 100 different ASICs More than 20 different designs in production (some are multi-ASIC) More than 2000 wafers (8-inch) produced! Designs for upgrades will use more advanced technologies: what is their radiation performance? Do we still need to use HBD for TID? ESE seminar, Jan2010F.Faccio23

Outline Radiation effects in CMOS technologies Influence of scaling Hardness-By-Design (HBD) Results in the 130nm generation TID In core transistors Characterization of the STI oxide In I/O transistors Guardrings Noise SEU Effects on reliability Results in the 90nm generation A quick look beyond 90nm ESE seminar, Jan2010 F.Faccio24

Test structures and measurement setup 3 commercial 130nm CMOS processes: foundries A,B and C (L.Gonella et al., “Total Ionizing Dose Effects in 130-nm commercial CMOS technologies for HEP experiments”, NIM A 582 (2007) 750-754) Study on 2 commercial 90nm CMOS is ongoing: foundries A and B Some are PMDs from foundry, some custom-designed test ICs NMOS and PMOS transistors, core and I/O devices (different oxide thickness), FOXFETs Testing done at probe station – no bonding required. Recently purchased equipment allows for the irradiation test at different T (down to -40C) Irradiation with X-rays at CERN up to 100-200Mrad, under worst case static bias ESE seminar, Jan2010F.Faccio25

Core NMOS transistors, linear layout (1) Wide transistors (W > 1  m): When the transistor is off or in the weak inversion regime: Leakage current appears (for all transistor sizes) Weak inversion curve is distorted ESE seminar, Jan2010F.Faccio26 Foundry A, 2/0.12 Narrow transistors (W < 0.8  m): An apparent Vth shift (decrease) for narrow channel transistors The narrower the transistor, the larger the Vth shift (RINCE) Foundry A, 0.16/0.12

Core NMOS transistors, linear layout (2) ESE seminar, Jan2010F.Faccio27 annealing pre-rad Foundry C Foundry A Effect on the leakage current Peak in leakage at a TID of 1-5Mrad Peaking dependent on dose rate and temperature, difficult to estimate in real environment Foundry B

Core NMOS transistors, linear layout (3) ESE seminar, Jan2010F.Faccio28 Effect on the threshold voltage Peak in Vth shift at a TID of 1- 5Mrad (A and C) The narrower the transistor, the larger the Vth shift (RINCE) Peaking dependent on dose rate and temperature, difficult to estimate in real environment Foundry C Foundry A Foundry B

Radiation-induced edge effects - NMOS ESE seminar, Jan2010 F.Faccio29 STI Depletion region + + + + + + Polysilicongate E field lines - - STI Depletion region Polysilicongate E field lines + + + + + + Oxide trapped charge - - - - Interface states V GS IDID 0 Main transistor Lateral parasitic transistor Peak leakage dependent on dose rate and temperature, difficult to estimate in real environment ! Characterization of trapping in STI needed! “RINCE” introduced at NSREC 2005 (F.Faccio and G.Cervelli, “Radiation induced edge effects in deep submicron CMOS transistors”, IEEE Trans Nucl Science, Vol.52, N.6, Dec2005, pp.2413-2420)

Core PMOS transistors, linear layout (1) No change in the weak inversion regime, no leakage An apparent Vth shift (decrease) for narrow channel transistors The narrower the transistor, the larger the Vth shift ESE seminar, Jan2010F.Faccio30 Foundry C, 0.28/0.12Foundry B, 0.14/0.13 Foundry A, 0.16/0.12

Radiation-induced edge effects - PMOS ESE seminar, Jan2010 F.Faccio31 STI Depletion region + + + + + + Polysilicongate E field lines - - STI Depletion region Polysilicongate E field lines + + + + + + Oxide trapped charge + + + + Interface states V GS IDID 0 Main transistor Lateral parasitic transistor

Core NMOS transistors, enclosed layout (ELT) As for the 0.25mm generation, the ELT structure eliminates all influence of the trapping in the STI oxide on the transistors The radiation hardness of the gate oxide is such that practically no effect is observed – verified for 2 foundries (A up to 140Mrad, B up to 30Mrad) Use of ELT and guardrings is safe but comes at a considerable cost. Is it necessary? ESE seminar, Jan2010F.Faccio32 Example: Foundry A

Necessity of ELTs ESE seminar, Jan2010 F.Faccio33 Case 1Case 2 Practically negligible increase of the leakage current. Use of ELTs is not needed AS LONG AS the natural radiation response of the technology is kept the same (need for monitoring regularly) Peaked increase of the leakage current. The evolution of the current depends on the properties of the traps responsible for this evolution (traps in the oxide and at the interface). Better knowledge of these traps – in the STI oxide – helps taking a decision. Also in this case, the results are valid AS LONG AS the natural radiation response of the technology is kept the same (need for monitoring regularly)

How to study the STI oxide (1) ESE seminar, Jan2010F.Faccio35 The technology we chose (Foundry A) is not insensitive to trapping in the STI oxide We should characterize the trapping properties in the STI at the edge of the transistors Difficulty: Current in the parasitic lateral transistor is in parallel to the (generally larger) current in the main transistor How to isolate the sidewall from the main transistor?

How to study the STI oxide (2) FOXFETs N-well source & drain Poly gate material W = 200  m L = 0.92 and 1.48  m Other FETs used different S/D diffusions (combination of n+ and n-wells) to simulate leakage in real ICs Custom-designed in a commercial 130 nm CMOS technology ESE seminar, Jan2010F.Faccio36

Study of STI oxide (1) Isochronal annealing This technique gives information on the energy of the traps Samples sequentially heated at increasing dwell T, then measured Interface traps anneal starting from 80 o C! ESE seminar, Jan2010F.Faccio37 Study done in 2006-2007 (in Foundry A) in collaboration with Vanderbilt and Arizona State University. F.Faccio et al., “Total ionizing dose effects in shallow trench isolation oxides”, presented at NSREC2007 and published in Microelectronics Reliability 48 (2008) 1000-1007 Charge pump measurements Frequency dependent CP measurements performed on irradiated samples. Difficult for FOXFETs with large V th (special setup available at Arizona State University) CP Signal decreases with frequency => dominant switching traps are interface traps Traps anneal from 80 o C!

Study of STI oxide (2) Peaked evolution of NMOS  V th and leakage is the balance of positive (in bulk STI) and negative (in interface traps) charge trapped. Negative charge trapping is good for radiation tolerance! Negative charge trapping occurs in interface traps annealing at T as low as 80 o C Resemblance with observations in bipolar oxides and early CMOS oxides at high TID What is the charge balance at dose rates typical of real applications? ESE seminar, Jan2010 F.Faccio38

Measurements at low dose rate Irradiation at 22 to 65rd(SiO 2 )/min at the ESA- ESTEC 60 Co facility FOXFET irradiated in same conditions Test also on 16kbit SRAM in same technology. Design with SRAM generator from commercial IP provider Low-Dose rate results much better!!!! It appears that, at room T, the simultaneous creation of interface states and anneal of trapped charge determine a very moderate increase in the leakage current. ELTs are not needed for most designs (and in particular for standard logic) ESE seminar, Jan2010F.Faccio39

I/O transistors, linear layout Large effect for all sizes, but more important for narrow channel transistors. Peaking of the leakage observed as for core transistors (STI is the same!) Results different with Foundry, but for all a large leakage is already measured at TID levels of the order of 50-100krad (NMOS) ELTs show relevant Vth shift, evidencing radiation effects in the gate oxide itself! Can the “standard” I/O libraries be used for our applications in LHC upgrades? How relevant is the leakage in I/O cells? Does it affect functionality? ESE seminar, Jan2010F.Faccio41 Foundry A, NMOS 0.36/0.24 Foundry A, PMOS 2/0.24

Irradiation of I/O cells Experimental results available only for small test circuits with limited number of I/O pads (5-6) Leakage increase in agreement with measurements on individual transistors. Functionality always preserved. ESE seminar, Jan2010 F.Faccio42 Pre-rad annealing Example of supply current for the periphery (I/Os) of a test chip containing shift registers. Courtesy of S.Bonacini

Are guardrings systematically needed? (1) ESE seminar, Jan2010 F.Faccio44 Use of FoxFETs with different drain-source electrodes is useful to answer the question Structures available only for Foundry A 1. N+diffusion to N+diffusion (source/drain of two neighbor NMOS transistors)

Are guardrings systematically needed? (2) ESE seminar, Jan2010 F.Faccio45 2. N+diffusion to Nwell (Nwell with PMOS logic to drain/source of NMOS logic) SUBSTRATE N+ diffusion STI OXIDE S N+ WELL CONTACT N WELL D Metal 1 G + + + + + STI oxide SUBSTRATE STI OXIDE S S N+ WELL CONTACT N WELL D N+ WELL CONTACT N WELL D Metal 1 G + + + + + STI oxide Vg=2.5V

ESE seminar, Jan2010 F.Faccio46 Without guardringPartial guardringFull guardring Are guardrings systematically needed? (3) Vdd N-well Vdd N-well Realistic test structure with series of Inverters + DFF along 350um, and with different separation between n-well (PMOS logic) and NMOS:

Are guardrings systematically needed? (4) ESE seminar, Jan2010 F.Faccio47

TID effect on the noise performance (1) Study in collaboration with Universities of Pavia and Bergamo (It), on custom samples in Foundry A. Similar data with very comparable results exist for Foundry B. Large NMOS and PMOS transistors with W=1mm and L=0.12, 0.24 and 0.48  m have been studied. Irradiation performed with X-rays up to 100Mrd. Conclusion: only NMOS transistors with L=0.12mm show any increase of the noise (1/f noise only, and only for small current densities). For all other cases, the noise performance is unaffected by TID. ESE seminar, Jan2010 F.Faccio49

TID effect on the noise performance (2) ESE seminar, Jan2010 F.Faccio50 - M.Manghisoni et al., “Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics”, IEEE TNS Vol.55, n4, August 2006, p.2456 - V.Re et al., “Total Ionizing Dose Effects on the Noise Performances of a 0.13  m CMOS Technology”, IEEE TNS Vol.55, n3, June 2006, p.1599 - V.Re et al., “Review of radiation effects leading to noise performance degradation in 100 - nm scale microelectronic technologies”, in 2008 IEEE NSS conference record, p.3086

Summary of results in 130nm Technologies from different Foundries have considerably different radiation tolerance (in particular, leakage of NMOS transistors) In our chosen technology (Foundry A), annealing of oxide trapped charge and activation of interface states in the lateral STI favorably affect the radiation tolerance at room T and real dose rates. Measurements at -30C should soon be available – this is a T closer to the one foreseen for the application in SLHC trackers A report summarizing all results on Foundry A – including guidelines for ASIC designers – is available on request Baseline solution: use of standard libraries for digital design This seems reasonable on the basis of our transistor-level measurements Unfortunately, we have no or very little data available on real complex digital circuits (with a large number of I/Os) to confirm our assumptions Need to regularly monitor the natural radiation tolerance of the process ESE seminar, Jan2010 F.Faccio51

Regular monitoring of the natural radiation tolerance – Foundry A Identical measurements performed on the same test chip manufactured in MPW runs far away in time (delivery to CERN in Nov04, Feb06 and May07) Overall, radiation performance is well comparable for core and I/O transistors, FOXFETs and diodes ESE seminar, Jan2010 F.Faccio52 Example for leakage current of core NMOS transistors for the 3 different manufacturing lots

Outline Radiation effects in CMOS technologies Influence of scaling Hardness-By-Design (HBD) Results in the 130nm generation TID In core transistors Characterization of the STI oxide In I/O transistors Guardrings SEU Effects on reliability Results in the 90nm generation A quick look beyond 90nm ESE seminar, Jan2010 F.Faccio53

SEU sensitivity: available data With the decrease of both Vdd and the node capacitance, we expect larger sensitivity to SEU in 130nm with respect to what we used to see in 250nm (where we used ELTs and guardrings!) Available data used to estimate error rates and (sometimes) compare them with 250nm data: “standard” SRAM and FF (from commercial library) several “hardened” cells ESE seminar, Jan2010 F.Faccio54

Available radiation data for “standard” SRAM cells (Foundry A) SRAM cells designed either by the Foundry or custom using a SRAM generator from a commercial provider ESE seminar, Jan2010 F.Faccio55 Irradiation done by CERN at PSI (CH) in 2002/2003 on Foundry-provided SRAM samples Irradiation done by CERN at LNL (It) in 2005 on custom samples designed with Artisan SRAM generator (size of the memory: 16kbytes). Effect of bias irrelevant in the explored range.

Comparison with 250nm memory Comparison with 0.25  m memory (rad-tol design typically used in LHC designs!!): Cross-section of the commercial 130nm design 15-30 times larger in LHC environment ESE seminar, Jan2010F.Faccio56

Available radiation data for “standard” FF cells (Foundry A) ESE seminar, Jan2010 F.Faccio57 Standard FF Results from the FNAL group presented by J.Hoff in May 2006. “Standard” FF from Artisan library irradiated with monoenergetic protons (200MeV) at the Indiana University Cyclotron Facility, with devices operating as storage cells (no continuous clock). Measured cross section: 4.86 ∙10 -14 cm -2 bit -1 Results from the CERN ESE group presented at TWEPP07 and published in JINST. “Standard” FF from Artisan library irradiated with Heavy Ions at UCL-CRC (Be), in static (no clock) or dynamic (clocked) conditions. Extrapolation of results to a mono-energetic 200MeV environment yields a cross section of 2 ∙10 -14 cm -2 bit -1

ESE seminar, Jan2010 F.Faccio58 It is possible to estimate the error rate in LHC by using the cross-section data measured using the Heavy Ion beam. This gives the information on the sensitivity of the circuit. With this information and the estimate (from simulation) of the probability for energy deposition in LHC, it is possible to compute the “cross-section” of the SRAM and FF in the LHC environment. Detailed explanation of the procedure can be found in: M.Huhtinen and F.Faccio, NIM A 450 (2000) 155-172 Error rate projection for SRAM and FF (LHC/SLHC) (1) Estimate cross-section in LHC environment (cm 2 /bit) Pixel Outer trk Endcap ECAL Exp hall 2.9 x 10 -14 2.5 x 10 -14 2.6 x 10 -14 2.2 x 10 -14 SRAM FF 7.0 x 10 -14 6.0 x 10 -14 6.3 x 10 -14 5.2 x 10 -14

ESE seminar, Jan2010 F.Faccio59 Error rate in different locations of LHC experiments (ATLAS, CMS) Approximate at max luminosity, with cross-section = 2.8 x 10 -14 cm 2 /bit for the SRAM and 7x10 -14 cm 2 /bit for the FF Barrel; radius = 4 cm 12 cm 37 cm 52 cm 100 cm Flux (all hadrons E>20MeV) particles/cm 2 s Error rate (SEU/bit s) 5 x 10 7 5 x 10 6 2 x 10 6 1 x 10 6 5 x 10 5 1.4 x 10 -6 1.4 x 10 -7 5.6 x 10 -8 2.8 x 10 -8 1.4 x 10 -8 For SLHC, multiply the error rate by 5-10 depending on luminosity increase. For example: for a circuit with 100 bits, at 12 cm, we estimate about 1-2 errors/hour in SLHC Error rate projection for SRAM and FF (LHC/SLHC) (2) SRAM FF 3.5 x 10 -6 3.5 x 10 -7 1.4 x 10 -7 7.0 x 10 -8 3.5 x 10 -8

Available radiation data for “hardened” cells (1) Large range of “hardened” cells custom designed and tested (200MeV protons) by FNAL. Results presented by J.Hoff in 2006. Some of them have cross-section 3 orders of magnitude below the one measured for the Artisan cell TypeCross Section LBL Dice3.84e-17 cm 2 /bit RT Dice5.86e-17 cm 2 /bit RT Seuss1.03e-15 cm 2 /bit RT SR-ff3.85e-14 cm 2 /bit RT normal3.23e-14 cm 2 /bit TR Seuss4.7e-15 cm 2 /bit TR SR-ff8.91e-15 cm 2 /bit Hit1.59e-15 cm 2 /bit Liu2.69e-16 cm 2 /bit Dice4.55e-15 cm 2 /bit Seuss1.05e-14 cm 2 /bit SR-ff5.02e-14 cm 2 /bit Artisan4.86e-14 cm 2 /bit Normal5.63e-14 cm 2 /bit ESE seminar, Jan2010F.Faccio60

Available radiation data for “hardened” cells (2) “Modified” DICE latches custom designed and tested in 2007 by the CERN ESE group. They have been tested with Heavy Ions (UCL-CRC, Be) in both static and dynamic (clocked) mode. Results presented at TWEPP07 and published in JINST Dynamic: large dependence on incidence angle for low LET 1-2 orders of magnitude better than standard Artisan cells at high LET Static: errors found only at 1 LET and 1 cell (very low statistic). Limit  around 4 ∙ 10 -12 cm -2 bit -1 (but fluence too low!) ESE seminar, Jan2010 F.Faccio61 DICE cells custom designed and tested in 2008 by the ATLAS Pixel detector collaboration (results presented by M.Menouni at TWEPP 08). 3 different layouts integrated. Tests done with the CERN 24 GeV/c proton beam. Cross- section varies with layout but mainly around 2-3∙10 -16 cm -2 bit -1. This is 10 times larger than what measured by FNAL on the same design in 2006 (but different layout and proton energy).

Summary on SEE sensitivity The decrease of Vdd (from 2.5V to 1.5/1.2V), and the use of “standard” layouts (no ELTs, no guardrings) contribute to increasing considerably the error rate per bit in 130nm with respect to what we used to see in 250nm LHC circuits The error rate can efficiently be reduced to any reasonable target rate (dependent on the application) with design techniques, and work is ongoing in this area within our community: “hardened” memory/FF cells Redundancy Encoding Sensitivity to SEL Both the technology construction and the relatively small Vdd point to a low sensitivity to SEL, especially for a radiation environment dominated by hadrons Nevertheless, SEL sensitivity is known to be heavily design dependent. ASIC designers should hence always address SEL when laying out their circuits (use frequent substrate contacts, add partial/complete guardrings whenever possible, be careful to high resistivity regions) Sensitivity to SEGR will be discussed in a few slides…

Outline Radiation effects in CMOS technologies Influence of scaling Hardness-By-Design (HBD) Results in the 130nm generation TID In core transistors Characterization of the STI oxide In I/O transistors Guardrings SEU Effects on reliability Results in the 90nm generation A quick look beyond 90nm ESE seminar, Jan2010 F.Faccio63

Effects of TID on device reliability (1) With custom-developed test structures in Foundry A, the possible influence of TID on transistor reliability has been studied (main investigator, M.Silvestri, Padova University – in collaboration with CERN and Vanderbilt University) ESE seminar, Jan2010 F.Faccio64 Stress performed on fresh or irradiated samples (TID up to 136Mrd) for a long time, up to 10Ks, measuring device degradation: Vth, drain current, Subth slope, transconductance Stress: DC Vgs and Vds higher than nominal applied for long times, enhancing injection of hot carriers in the drain region Conclusion: irradiation worsens the behaviour of MOSFETs during hot-carrier stress for standard (linear layout) core transistors only – but effect is not dramatic. ELTs core transistors performance during stress is independent on previous TID irradiation. I/O transistors are more resilient to CHC stress if previously irradiated. Channel Hot Carrier (CHC) Stress on NMOS transistors M.Silvestri et al., “Channel Hot carrier Stress on Irradiated 130-nm MOSFETs”, IEEE TNS 55, n4, Aug. 2008, p.1960 M.Silvestri et al., “Degradation induced by X-ray irradiation and Channel Hot Carrier stresses in 130-nm NMOSFETs with enclosed layout”, IEEE TNS 55, n6, Dec.2008, p.3216

Effects of TID on device reliability (2) ESE seminar, Jan2010 F.Faccio65 Stress performed on fresh or irradiated samples (TID=1Mrd) of core transistors (not I/Os) Stress: increasing voltage (ramp) applied to the transistor’s gate. Ramp rate = 0.5mV/s from Vgs=3V. Time to fail (T FAIL ) is an indication of the resilience of the MOSFET, hence of the quality of the dielectric. Conclusion: irradiated samples show a longer TDDB (both NMOS and PMOS)! Time-Dependent Dielectric Breakdown (TDDB) M.Silvestri et al., “The role of irradiation bias on the Time- Dependent Dielectric Breakdown of 130-nm MOSFETs exposed to X-rays”, IEEE TNS 56, n6, Dec. 2009, p.3244

Effects of TID on device reliability (3) ESE seminar, Jan2010 F.Faccio66 Single Event Gate Rupture (SEGR) Heavy Ion Irradiation (LET=32MeVcm 2 mg -1 ) performed on fresh or irradiated samples (TID up to 100Mrd) Stress: increasing voltage (staircase from 1.5V, step 100mV) applied to the transistor’s gate during HI irradiation until breakdown occurs. BD identified as sudden increase in gate current. Conclusion: irradiated samples show a very similar (after 100Mrd) or slightly higher (after 3Mrd) voltage to breakdown. The rupture voltage lies far from operative conditions even when the devices were subjected to extremely high TID. M.Silvestri et al., “Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-ray Irradiation”, Presented at RADECs 2009, accepted for publication in IEEE TNS

Radiation effects in 90nm technologies Study of TID effects is ongoing for 90nm technologies from 2 suppliers (Foundries A and B) First set of result on PMD kindly provided by a supplier is available, while measurements of custom-designed test structures is taking place now (L.Pierobon for Foundry B, M.Bochenek for Foundry A). Some preliminary results will be shown. Measurements done on core and I/O transistors, both NMOS and PMOS Measurement procedure identical to the one used for 130nm (same equipment, same measurement setup, very similar set of custom structures) ESE seminar, Jan2010 F.Faccio68

Core transistors – Foundry A Increase of leakage current in NMOS transistors, with peak degradation around 1Mrd Dependence of leakage and Vth shift on channel length observed (for W, not enough structures available) Very small threshold voltage shift, even after large doses and for PMOS transistors ESE seminar, Jan2010 F.Faccio69 PMOS Study done by L.Gonella (ME). Internal report available NMOS

Core transistors – Foundry B Measurements still to be completed Increase of leakage current in NMOS transistors practically negligible (only 1 transistor, with LowVt, is an exception that has to be confirmed – it could be that the degradation is not due to radiation). TID radiation performance hence better than Foundry A (this was the same in 130nm) Vey small threshold voltage shift, even after large doses and for PMOS transistors ESE seminar, Jan2010 F.Faccio70 Study done by L.Pierobon (ME)). Internal report will be available when the work is completed

I/O transistors – Foundry A Data for Foundry A structures only Results for NMOS are not to be seen as “worst case” since bias during irradiation was limited to Vdd/2 or Vdd/3 for practical reasons Main TID effects: leakage current in NMOS and Vth shift in PMOS. Magnitude is nevertheless limited (to be checked in worst case bias for NMOS) ESE seminar, Jan2010 F.Faccio71 PMOS NMOS

Comparison 130/90 nm – Foundry A (1) Larger increase in leakage current for the 90nm, with peak occurring at smaller TID Smaller Vth shift in 90nm ESE seminar, Jan2010 F.Faccio72 PMOS Core transistors NMOS

Comparison 130/90 nm – Foundry A (2) Comparable leakage and much smaller Vth shift in NMOS (CAREFUL: bias conditions are more severe in 130nm) Much smaller Vth shift in PMOS (fair comparison) ESE seminar, Jan2010 F.Faccio73 PMOS I/O transistors NMOS

Other efforts in HBD in 90nm Arizona State University (ASU) is developing library and building blocks in a 90nm commercial technology (Foundry A) under a contract with Air Force Research Labs (AFRL) Results for a Cache Memory and BIST error-protected engine were presented at RADECS09. Static current increases in this 5x5mm chip by 37% after 3.2Mrd (attributed to an on-chip unhardened PLL) ASU reported previously a 131x static current increase for an unhardened SRAM at 1Mrd in the same technology ESE seminar, Jan2010 F.Faccio74 - D.Pettit et al., “High Speed Redundant Self-correcting Circuits for Radiation Hardened By Design Logic”, to be published in the proceedings of the RADECS09 conference and (possibly) in IEEE TNS - X.Yao et al., “A 90 nm Bulk CMOS Radiation Hardened by Design Cache Memory”, to be published in the proceedings of the RADECS09 conference and (possibly) in IEEE TNS

A quick look ahead In the optimistic hypothesis where we will be able to afford 65nm CMOS or beyond, what the radiation effects could look like? TID As long as SiO 2 remains the dominant gate insulator material, with thickness in the 1-2nm range, radiation response will be determined by the STI oxide. This, we have seen, varies (at least) with the manufacturer When moving to high-K dielectrics, radiation effects in the gate insulator could be different… but no data on commercial processes exist so far (to my knowledge) SEEs The presentation of STM a few months ago already gave us a flavor of the possible situation with SEU: with respect to 130nm the cross-section per bit should be smaller, but the error rate could easily be dominated by multiple bit error. Designs will have to accurately take this into consideration For destructive events, there is no evidence that they could get worse ESE seminar, Jan2010 F.Faccio76

Summary A vast, but not complete, set of data on the radiation effects in 130nm CMOS is available TID effects measured at the transistor level indicate the possibility to work without a dedicated HBD library This has to be verified with radiation tests at -30C, and on representative full digital circuits SEU sensitivity has been measured and estimated error rates in a SLHC-like environment have been calculated Designers should be aware of the increased sensitivity and use appropriate techniques to reach system-level design goals (but this is not new, since these techniques were used in the LHC generation of ASICs) Radiation does not worsen gate oxide reliability, and SEGR threshold is far from the application voltage Extra care has to be taken to reduce possible sensitivity of ASICs to SEL (now that guardrings are not systematic anymore) – at least for full custom. For standard logic, measurements on a representative full digital circuit should determine the threshold for the SEL to be triggered Measurements on 90nm technologies are ongoing, and indicate TID tolerance generally better than for the 130nm

Particles and damages ESE seminar, Jan2010F.Faccio78 RadiationTIDDisplacement (NIEL)SEE X-rays 60 Co  Expressed in SiO 2 Almost identical in Si or SiO 2 No pEquivalences in Si $ @60MeV 10 11 p/cm 2 =13.8krd @100MeV 10 11 p/cm 2 =9.4krd @150MeV 10 11 p/cm 2 =7.0krd @200MeV 10 11 p/cm 2 =5.8krd @250MeV 10 11 p/cm 2 =5.1krd @300MeV 10 11 p/cm 2 =4.6krd @23GeV 10 11 p/cm 2 =3.2krd Equivalences in Si $,* @53MeV 1 p/cm 2 = 1.25 n/cm 2 @98MeV 1 p/cm 2 = 0.92 n/cm 2 @154MeV 1 p/cm 2 = 0.74 n/cm 2 @197MeV 1 p/cm 2 = 0.66 n/cm 2 @244MeV 1 p/cm 2 = 0.63 n/cm 2 @294MeV 1 p/cm 2 = 0.61 n/cm 2 @23GeV 1 p/cm 2 = 0.50 n/cm 2 Only via nuclear interaction. Max LET of recoil in Silicon = 15MeVcm 2 mg -1 nNegligibleEquivalences in Si $,* @1MeV 1 n/cm 2 = 0.81 n/cm 2 @2MeV 1 n/cm 2 = 0.74 n/cm 2 @14MeV 1 n/cm 2 = 1.50 n/cm 2 As for protons, actually above 20MeV p and n can roughly be considered to have the same effect for SEEs Heavy IonsNegligible for practical purposes (example: 10 6 HI with LET=50MeVcm 2 mg -1 deposit about 800 rd) NegligibleYes $ Energy here is only kinetic (for total particle energy, add the rest energy mc 2 ) * The equivalence is referred to “equivalent 1Mev neutrons”, where the NIEL of “1MeV neutrons” is DEFINED to be 95 MeVmb. This explains why for 1MeV neutrons the equivalence is different than 1

Radiation effects in deep submicron CMOS technologies Federico Faccio 1.

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Radiation effects in deep submicron CMOS technologies Federico Faccio 1.

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