Leo Greiner IPHC testing Sensor and infrastructure testing at LBL. Capabilities and Plan

Leo Greiner IPHC testing Talk Structure Existing capabilities and current status. (More from MS) Testing boards including tests on individual sensors and infrastructure. Schedule

Leo Greiner IPHC testing Existing RDO and Test System 8 x 50 MHz ADC inputs (6 implemented) FPGA processing for CDS, etc. Full Frame readout Fiber optic readout to linux PC or readout via ethernet and NIOS on Stratix FPGA. All JTAG, clock, signal and other I/O are implemented over an RJ- 45 connector interface. Fully tested on the bench and in beam conditions at the ALS and at RHIC. Test Boards We have two complete systems of the type seen above.

Leo Greiner IPHC testing Testing Boards Mimostar-3 individual test card (FR4) Mimostar-2 individual test card (FR4)- optional Mimosa-22E individual test card (FR4) Mimostar-3 infrastructure test board (FR4 with optional flex) Phase-1 individual test card (FR4) Phase-1 test cable (FR4 and flex) PCBs needed for the next year of testing All in addition to the new motherboard and RDO system

Leo Greiner IPHC testing Mimostar-3 individual test board Individual Mimostar-3 sensor. Interfaces with existing RDO system. Almost identical circuit to IPHC test board Status: Layout complete – board is being fabricated. Full thickness and thinned 50 micron Mimostar- 3 sensors will be tested. We will test: Sensor operation, noise, pixel response.

Leo Greiner IPHC testing Mimostar-2 test boards Mimostar-2 telescope Used in ALS and STAR tests High noise due to un-terminated DAC outputs only one test assembly Mimostar-2 individual mezzanine test card Equivalent noise to IPHC design, (DACs can be terminated) Previous generation design, needs adapter to fit existing RDO system Additional PCBs will require a new fabrication. If circumstances require, we can make a new Mimostar-2 test board based on the Mimostar-3 layout. We believe that we are finished with testing on Mimostar-2.

Leo Greiner IPHC testing Mimosa-22E individual test board Interface to the existing test system. This will be the first digital output sensor to which we have access. This will be used to tune our RDO system for interfacing to the sensor as well as evaluating sensor performance. We expect that IPHC will perform extensive testing on this sensor, we would perform functional and speed tests and other testing as needed.

Leo Greiner IPHC testing Mimostar-3 Infrastructure test board Early prototype cable with 40 differential pair output, clock and control routed under sensor area. Mimosa-5 thinned to 50 um. 10 sensor PCB with (removable) full capacitive bypassing and filtering. Fabrication in FR-4. Test thinned 50 um sensors Validate 10 sensor infrastructure. Test LVDS multi-drop clock, JTAG, markers, crosstalk, sensor interaction, power dissipation, bandwidth limits (useful as a check of conductor geometry and impedance for later generation Phase MHz LVDS outputs) We intend to cool this board for testing to give improved noise performance.

Leo Greiner IPHC testing Phase-1 Individual test board Interface to new RDO system. Test thinned 50 um and full thickness dies. Small scale infrastructure tests (bypassing, etc.) before design of 10 sensor infrastructure test board.

Leo Greiner IPHC testing Phase-1 Cable (FR-4 and flex) 10 sensor PCB optimized for detector function and low mass. Two stage development – test with FR-4 version and build final copper conductor flex kapton cable (Al conductor to follow). Test and characterize all individual and system functionality with the new RDO system.

Leo Greiner IPHC testing Phase-1 Probe testing system This is not yet well defined. We would like to verify that the capabilities of our existing RDO system are sufficient for this task since we intend to use this as the basis of the probe test system. This will require further consultation.

Leo Greiner IPHC testing Summary Testing will be a large component of the effort needed for the STAR HFT for the next year (or two). Similar testing capability is needed at both LBNL and IPHC. Question – Can we combine efforts on the testing boards needed and make common hardware where practical? (i.e. Mimosa-22e, Phase-1 and Probe test card) Detailed testing program needs to be developed in collaboration with IPHC.

Leo Greiner IPHC testing Schedule Missing dependency Moves start of this task to August

Leo Greiner IPHC testing Detailed System Structure – RDO Board(s) New motherboard Two board System – Virtex-5 Development board mated to a new HFT motherboard Xilinx Virtex-5 Development Board Digital I/O LVDS Drivers 4 X >80 MHz ADCs PMC connectors for SIU Cypress USB chipset SODIMM Memory slot Serial interface Trigger / Control input FF1760 Package 800 – 1200 I/O pins 4.6 – 10.4 Mb block RAM 550 MHz internal clock Note – This board is designed for development and testing. Not all features will be loaded for production.

Leo Greiner IPHC testing fin