Memory Addressing in Linux  Logical Address machine language instruction location  Linear address (virtual address) a single 32 but unsigned integer  Physical address address in memory chip

Logical address translation Logical address Segmentation Unit Paging Unit Linear AddressPhysical Address

Segmentation in Linux  Linux uses segmentation only when required by the 80x86 architecture  All processes use the same logical addresses  All segments descriptors are stored in the Global Descriptor Table  Segments used by Linux Kernel code segment  DPL = 0 (Kernel Mode)  Type = 0xa(read and execute) Kernel data segment  DPL = 0  Type = 2 (read and write) User code segment  DPL = 3 (User Mode)  Type = 0xa User data segment  DPL = 3  Type = 2 Task State Segment (TSS) Default Local Descriptor Table (LDT) Advanced Power Management (APM)  4 segments

Paging in Linux  In 80x86 processors, paging is enabled by setting the PG flag of a control register named cr0. When PG = 0, linear addresses are interpreted as physical addresses When PG = 1, physical addresses are computed from the page table  The 32 bits of a linear address are divided into three fields: Directory  most significant 10 bits Table  intermediate 10 bits Offset  The least significant 12 bits

Paging in Linux (80x86) DirectoryTableOffset cr3 Page + Page Table Page Directory

Extended Paging (Pentium) DirectoryOffset cr3 Page + Page Directory + 4 MB Enabled by setting the PSE flag of the cr4 register

Three-Level Paging  Used in 64-bit architectures  HP Alpha Page frames are 8kb offset field is 13 bits Only the least significant 43 bits of an address are used Three-levels of page tables  3 10-bit page tables

Physical Address Extension (PAE) Paging Mechanism  Kernel cannot directly address more than 1 GB of RAM  Starting with the address pins = 64 GB  Pentium Pro Physical Address Extension (PAE) Set PAE flag in the cr4 control register

Change to Paging Mechanism to support PAE  64 GB split into 2^24 distinct page frames  page tables expanded from 20 to 24 bits  new level of page table called page directory pointer table (PDPT)  cr3 control register contains a 27-bit Page Directory Pointer Table base address  When mapping 4KB pages (ps flag cleared) cr3 -> PDPT bits 31-30: one of 4 entries in PDPT bits 29-21: one of 512 entries in Page Directory bits 20-12: one of 512 entries in Page Table bits 11-0: Offset  When mapping 2MB pages (ps flag set) cr3 -> PDPT bits 31-30: one of 4 entries in PDPT bits 29-21: one of 512 entries in Page Directory bits 20-0: Offset

Hardware Cache  Use the CD flag of the cr0 processor register to enable cache  Each page can have a different cache policy  Page Directory and each page table entry includes two flags PCD (page cache disable) PWT (page write-through)  Each 80x86 processor has its own local TLB – located in cache

Loading Linux  Linux kernel is installed in RAM starting from 0x (2 nd megabyte)  typical configurations give a kernel size < 2MB  BIOS uses first meg

Process Page Tables  linear addresses from 0x to 0xbfffffff either user or kernel mode  linear addresses from 0xc to 0xffffffff can only be addressed in kernel mode  PAGE_OFFSET = 0xc

Kernel Page Tables  The kernel maintains a set of Page Tables for its own use rooted at the Master Kernel Page Global Directory  After system initialization This set of page tables never used directly The highest entries are the reference model for the corresponding entries of the PGD of every regular process in the system

Provisional kernel page tables  initialized statically during kernel compilation  during initialization need to be able to first 8megs are accessed directly  But were using paging So an identity mapping is performed

Fix-Mapped Linear Addresses  The 4 th gigabyte is reserved for a direct mapping of physical memory  a fixed mapped linear address is a constant linear address like 0xfffffdf0 whose corresponding physical address can be set up in an arbitrary way  Linear address X maps to physical-Address X- PAGE_OFFSET

Noncontiguous Memory Area Management  It is preferable to map memory areas into sets of contiguous page frames  However, if requests for memory areas are infrequent, it makes sense to use an allocation schema based on noncontiguous page frames accessed through contiguous linear addresses  Linux uses noncontiguous memory areas in several ways Ex: to allocate data structures for active swap areas

Linear addresses interval Physical memory mapping vmalloc area vmalloc area Persistent kernel mappings Fix-mapped linear addresses PAGE_OFFSET high_memory 4 GB PKMAP_BASE VMALLOC_END 8 MB4KB VMALLOC_START high_memory = linear address that corresponds to the end of directly mapped physical memory