1. Introduction to Virtual Memory and Memory Management
ARM
Advanced RISC Machines
Revision History
Revision Modifications Changed By
1.0 Initial issue Bryn Parry

2. Physical Memory
A computer system will probably contain several different types of memory devices.
The Memory Management mechanism must access all available memory in, apparently , the same way as seen by user code.
Physical Address Space
DISC
or other v. slow
device
Fast memory, on chip or off, is expensive.
Most memory will be slow (eg disc)
Making the system think all memory is in the one place, and of the one type employs Virtual Memory.
Memory
Whether of Von Neumann or Harvard architecture, a system will probably contain several types of memory, from fast to slow RAM and ROM (e.g.. BIOS), through disc to optical media. While the ideal implementation for a memory system would be both fast and cheap, in reality these two attributes are usually mutually exclusive. So, the different memories will be chosen usually as a compromise between speed, size, power and cost.
Two criteria may quantify a memory device’s speed:
• Latency : the time taken for the memory to return the first word of date. Note that the memory space may be made up of devices with differing widths(e.g. 1x64Kb,8x8Kb)
• Bandwidth : the rate at which data can be returned to the CPU, once the initial flow has been established.
The amount of fast memory which can be employed is usually determined by cost. We will see in the next module how to optimise the use of this limited resource by using a cache structure.
However, the total size of main memory required by an application may also be larger than the physical memory available. This situation is not catastrophic, as not all instructions and data need to be resident in main memory at the same time. We must therefore maintain the “illusion” that they are, in a large VIRTUAL memory.
Slow
D/VRAM,ROM
Fast SRAM,ROM

3. = Virtual memory * The physical memory may be smaller than the
- total CPU address space
- the total required for all user code and data.
* Create a VIRTUAL memory space, mapping into the Physical memory space.
Physical Address Space
Virtual Address Space
DISC
or other v. slow
device
Virtual
Memory
Seen by the
system.
e.g. 4GB
e.g.. 180MB
4MB
1MB =
Slow
RAM/ROM
Virtual memory
The task of producing the “illusion”, that the varied physical address space appears to be a larger, contiguous area of identical devices is usually given to a Memory Management Unit ( an MMU). When a reference to a virtual address is raise the MMU must check that the corresponding physical address exists, is accessible with the current privilege level, and then provide the actual physical address.
This mapping, or translation, from a virtual to a physical address is accomplished by using translation tables kept in main memory.
So, the MMU or memory management mechanism must be able to resolve a request to access a particular segment of virtual memory, whatever type of memory mechanism (S/D/VRAM,ROM,disc) is being employed.
Fast RAM/ROM

4. Virtual Addresses
Mapping of virtual addresses to physical addresses via a page table
Memory mapping or address translation
Virtual Page Number
Page Offset
Main Memory
Page Table
Physical Address

5. Memory management -overview
"Memory Management Units" allow the processor to use external memory mapped into a virtual address space.
allows protection schemes to be implemented
control system when the physical memory is less than the virtual memory
control system when physical is greater than the virtual memory
Efficient memory usage ( Eg: defragmentation )
This added complexity may bring problems:
increased die size
a “single” access may require up to three accesses to translate the address and get the data.
Memory management - overview
The physical memory could be less than the virtual memory if for an example an 8bit processor was trying to manage 4MBytes of memory.
While complex memory mapping may not be needed in some systems (e.g. embedded systems) access protection almost certainly will. Being able to integrate a MMU on-chip also provides the usual advantage of speed.

6. An example Translation and checking mechanism.
The Memory Management hardware resolves:
the mapping from virtual to physical memory
the access rights of the current process against those of the memory requested.
Translation
and checking
mechanism.
Virtual
Memory
Physical
Memory
Process C
MMU
Process B
TLB
VRAM
Process A
Translation Tables
RAM
Memory management - example
The purposes behind memory management are twofold:
a. The resolution, or mapping, of addresses for code or data required by a process, from the virtual memory space the process works in, to the physical memory that actuallyto access.
The provision of these facilities requires look-up tables for the translation, which are kept in main memory. Retrieving the address from such tables will take one access for a Section, and two for Pages, before the access to the physical location can be made.
However, an on-chip cache of the 32 most recently translated addresses, and their translation, are kept in the Translation Look-aside Buffer to make the most of previous translations.
ROM
Manager
RAM
RAM
Protection
& Aborts

7. Page Tables
Page tables contain the mapping of the Virtual to Physical Addresses
The Page table must be read before the translation can take place
Extra read cycles are required to access the page tables
A single read could require up to 3 accesses to memory to get the data 31
Page Table Entry
Address Mapping
Protection
The amount of information that can be stored
about the protection is limited by the size of the page.

8. Segments and Pages
Memory (physical or virtual) is divided into Segments or Pages
Segments are variable size blocks
Largest segment could be 4GBytes
Smallest segment could be 1 Byte
Requires two words per address
More difficult to handle as must find contiguous unused block of memory to replace a segment
Pages are fixed length blocks
Typically 512 to 8192 bytes
Require one word per address
Easier to handle as all blocks are the same size
Less wasted storage space as it is easier to store the smaller pages
Compromise is Paged Segments
Each segment is is an integral number of pages
As segments could be as small as one byte up to 31 bits of data would be needed to re-map the byte somewhere else. Any protection information would have to go into a second word of data.
Segments are more complicated as the program needs to know where they start and what size they are.
Pages do not need as much information. The unused part of the mapping can be used for the protection information.

9. Memory management structures
Two main operations are required from a memory management system:
Translation : Finding the location of the real, physical, address of the required memory from the virtual address.
Protection : Confirmation that this location is eligible for access under the current privilege
ARM has split the two operations. This allows the size of the units of address location or translation to be different from those of protection
Virtual Address
The MMU
Translation/Protection
Physical Address
Exception
The tasks of a memory management system
The process of locating and accessing a physical memory location, given a logically consistentTRANSLATION.
This must take into account the organisation of the memory, and its granularity, that is the arrangement and size of blocks of the address space used. It may also have to deal with data and instructions being relocated. The simplest mechanism for translating one such set of coordinates into another is via a look-up table which could contain either some function from which the address could be calculated, or better still the address itself.
Locating the data is one of the major tasks, but the location (containing code or data) may actually be protected from access by the CPU unless it is in a specific mode. Checking on the access rights to the location before going through the fetch saves time. This is the task of:
PROTECTION.

10. Translation Lookaside Buffers ( 1 )
A data read could take up to three accesses to memory
Slow when trying to read data
Data Required
Access Real Data
Page Tables
descriptor 2
The Translation Look-aside Buffer (TLB)
The TLB is used to cache virtual memory address locations already translated to physical memory address, and return the location in main memory. The retrieval operation is as follows:
a. Access to users (i.e. virtual) address space is requested.
b. The contents of the TLB are checked to see if any entries correspond to this address. Remember, these are the addresses, in virtual memory, of the locations in main memory for which a translation already exists.
c. If the requireda hit) then the address in physical memory of the required location is returned, and the access to that address in memory is made.
d. If the requested page has not been accessed previously in to main memory then there will not be a TLB location corresponding to the required address. This(a miss) will cause a trap to the translation mechanism, which will address the required location into memory, update the registers in the TLB, and return to the user program.
In fact the translated addresses of the last 32 memory accesses are kept, in the Translation Look-aside Buffer. As this is on-chip it speeds up considerably the process of issuing a physical address from a required virtual reference. Only if the TLB misses is the translation table walk hardware invoked to retrieve the information from a translation table in physical memory.
Once retrieved, the translation information is placed into the TLB, possibly overwriting an existing entry. The entry to be overwritten is chosen cyclically.
Physical Memory
descriptor 1
MMU
Virtual Memory

11. Translation Lookaside Buffers (2 )
The Translation Lookaside Buffers effectively cache the last transactions so the accesses to the page tables are not needed.
TLB’s
Access Real Data
Page Tables
By cacheing the last N translations the accesses to the page tables are avoided and the whole process can be speeded up.
Typically there are 32 TLB’s in a processor.
Physical Memory
MMU
Virtual Memory

12. The Translation Page Tables
If the TLB misses, the translation walk hardware accesses the Translation Page Tables, kept in physical memory
The translation will be satisfied
Physical memory
Translation Tables (in physical memory)
Sector Access
Translation
Table
(level 1)
To MMU
Translation
Table
(level 2)
Base of Translation Table held in TT Base Register of MMU.
Must reside on 16KByte boundaries
Translation information returned to TLB.
Page access
L2PT
Translation Tables
The Translation Tables are maintained in main memory, and support two levels of indirect addressing. The base address of the Level One Page Table (L1PT) is held in the Translation Table Base register in the MMU. As this address is formed by the 18 high-order bits (13-0 are zero) the L1PT must reside on a 16KB boundary.
This base address is concatenatedtaken from the high-order 11 bits in the virtual address, to provide the index (or offset) into the 4KB table.
From this location a four-byte L1PT entry will be returned, which is called the Level One Descriptor.