G. Parès – A. Berthelot CEA-Leti-Minatec GU project status

© CEA. All rights reserved LETI proposal | 2  Objectives :  To supply thin wafers in order to test the dicing & the stacking of a detector on read out chip for ATLAS experiment  Project requirements :  Process on FE I4 functional wafers / 200 mm  Need to have interconnects between ROIC and detector  µbumps  Thin ROIC required  100 µm  Wafers debonding  Dicing & detector stacking will be done by Advacam (SME, spin-off of VTT)  Wafers bow measurements done by Scottish Microelectronic Center (SMC), GU leading  Incoming wafers  Wafer diameter: 200mm  Wafer thickness: ~725um  IC Technology: 130 nm / IBM  Number of wafers provided: 10 Customer initial requirements Final component 100 µm

© CEA. All rights reserved LETI proposal | 3 Process flow proposal – Runs 1 & 2 Taping & delivering to SMC for bow measurements Incoming wafers Temporary bonding Debonding Front side µbumps Thinning to 100 µm RUN 1 : delivering of two wafers to Advacam RUN 2 : delivering of two debonded thin wafers to SMC

© CEA. All rights reserved LETI proposal | 4 Process flow proposal – Run 3: R&D Incoming wafers Temporary bonding Debonding Front side µbumps Thinning to 100µm or more if needed Stress compensation layer RUN 3 : delivering of two debonded thin wafers + stress compensation layer to SMC Taping & delivering to SMC

© CEA. All rights reserved LETI proposal | 5 Process flow proposal – Runs 4 & 5 : R&D Debonding Thinning to 100µm or more if needed Optimized Stress compensation layer RUN 4 : delivering of two debonded thin wafers + stress compensation optimized layer to SMC Taping & delivering to SMC RUN 5 : delivering of two debonded thin wafers + stress compensation optimized layer to Advacam

© CEA. All rights reserved LETI proposal | 6  Technical proposal  Layout of Micro-bumps level  RUN 1 : Delivery to Advacam of two FE I4 wafers with µbumps on front side / without thinning (725 µm)  D1  RUN 2 : Delivery to SMC of two FE I4 thinned wafers (100 µm) + µbumps on front side – D2  RUN 3 : Delivery to SMC of two FE I4 thinned wafers + backside stress compensation + µbumps on front side  D3  RUN 4 : Delivery to SMC of two FE I4 thinned wafers + Optimized backside stress compensation + µbumps on front side  D4  RUN 5 : Delivery to Advacam of two FE I4 thinned wafers + Optimized backside stress compensation + µbumps on front side  D5  Optimized thickness of Si will be adapted after run2 if needed (150µm possible).  Stress compensation layer will be chosen in the LETI materials according to SMC wafer bow/warpage measurements / One single trial, no specific stress study.  Every functional wafers will be chipped with dummies wafers.  LETI needs :  GDS files of FE I4 chips : top metal & passivation  FE i4 Wafer mapping / wafer step plan  Layer table  Ten FE I4 wafers (10) LETI proposal

© CEA. All rights reserved LETI proposal | 7  Proposed planning / 8 months duration Planning & deliverables proposal  Deliverables :  D1 : µbumps GDS files + 2 FEI4 wafers (725µm) with µbumps on front side  D2 : 2 thinned FEI4 wafers to 100 µm with µbumps on front side / debonded on tape  D3 : 2 thinned FEI4 wafers to 100 µm with µbumps on front side + stress compensation layer / debonded on tape  D4 : 2 thinned FEI4 wafers to 100 µm with µbumps on front side + optimized stress compensation layer / debonded on tape  D5 : 2 thinned FEI4 wafers to 100 µm with µbumps on front side + stress compensation layer / debonded on tape / Advacam

© CEA. All rights reserved LETI proposal | 8  Financial proposal :  µbumps design, layout & mask  3D technology on ten FEI4 wafers provided by Glasgow University including :  µbumps on front side  Temporary bonding  Si thinning  Stress compensation layer implementation  Debonding & taping  Shipping to SMC and Advacam  Five different runs  Total price : €  Payment conditions :  /03/2013  the end of the project Financial proposal

© CEA. All rights reserved LETI proposal | 9 RUN1 results  2 wafers with copper µbumps  Start date = 8/03/13  Shipping date to advacam = 23/04/13 Incoming wafers Front side µbumps RUN 1 : delivering of two wafers to Advacam

© CEA. All rights reserved LETI proposal | 10 Process Flow -Control -Back side and front side cleaning -Preclean + seed layer deposition Ti 100nm + Cu 400nm -Photolithography « µBump », negative photoresist -Flash O2 -ECD Cu 10µm + SAC 8µm -Stripping -Cu 400nm + Ti 100nm wet etch -SAC reflow

© CEA. All rights reserved LETI proposal | 11 Control before process  2 wafers provided by Glasgow university  Control before process: some particles have been observed  A front side specific cleaning has been performed  number of particles decreased Observations before process

© CEA. All rights reserved LETI proposal | 12 µBump litho  The position of alignment marks designed by LETI is not correct  Alignment of µbump level has been performed on the metal pads directly  OK  µbump diameter=30µm Observations after the photolithography step

© CEA. All rights reserved LETI proposal | 13 µBump ECD Cu-SAC  ECD Cu 10µm + SAC 8µm  Strip + µbump height measurements:  P24: mean=17.33µm – unif = 3.18%  P25: mean=17.48 – unif=4.08% µbumps height measurements after ECD step (wafer map on the 2 wafers)

© CEA. All rights reserved LETI proposal | 14 µBump after SAC reflow  Seed layer etch + SAC reflow  2 probes resistance measurement =~2.5 Ohm on 2 µbump chain on top metal Observations after SAC reflow

© CEA. All rights reserved LETI proposal | 15 RUN2/3 status  4 wafers with copper µbumps + temporary bonding + thinning 100 µm + stress compensation (run 3)  Start date = 12/04/13 (1 month delay vs RUN1)  Incoming inspection = some big particules  Current status seed removal after µbump Cu/SAC ECD  Short loop with µbumps/Si monitors for temporary bonding and thinning setup in progress

© CEA. All rights reserved LETI proposal | 16 Control before process  4 wafers provided by Glasgow university  Control before process: some particles have been observed  A front side specific cleaning has been performed  number of particles decrease Observations before process Al Pad ok P22 = VUAYCRH (particles) P23 = ABPJXGH P24 = V7B8WTH P25 = VKB8WFH (particles) P22 P25 P24

© CEA. All rights reserved LETI proposal | 17 µBump litho Observations after the photolithography step T1 P22 P24  Few Spin on defects  Alignment is acceptable

© CEA. All rights reserved LETI proposal | 18 µBump ECD Cu-SAC  ECD Cu 10µm + SAC 8µm  Strip + µbump height measurements:  P22: mean=17.33µm – unif = 3.12%  P23: mean=16.74µm – unif = 4.08%  P24: mean=16.65µm – unif = 4.77%  P25: mean=17.39 – unif=5.19% µbumps height measurements after ECD step (wafer map on the 2 wafers) µbump height a little bit too low on P23 and P24

© CEA. All rights reserved LETI proposal | 19 µBump after seed etch P22 and P25: -seed layer etching is completed -Issue with black Alu Pad => electrical test betwen two pads done => contact is still OK P23 and especially P24: -seed layer etching is not completed on some dies: remains of cupper and Ti -Issue with black Alu Pad => electrical test betwen two Pads done => contact is still OK P24 Black Al Pad Cu Ti? P23

© CEA. All rights reserved LETI proposal | 20 Conclusion  P22 and P25 have black Alu pads but the seed etch is completed and contact between two pads are good.  P23 has a few dies with seed etch issue  P24 has more seed etch issues than P23.  Next time we can try a Ti etch with SC1 solution instead of HF.

© CEA. All rights reserved LETI proposal | 21 Bonding & thinning (run 3&4)  Split 1 wafer each run between slide off/ZB  Bow measurement done at SMC prior to debonding  Slide off debonding done by EVG  send back to SMC without tape (?)  ZB debonding done at Leti on frame/tape  send to SMC

© CEA. All rights reserved LETI proposal | 22 New context for stress compensation study  Leti consider that SMT bow measurement will not provide relevant results for stress compensation based on thin wafer measurement (100 µm)  Measure will be very difficult due to the flexibility of the wafer and also the high warpage  Repeatability of the measure (2 wafers) may be not sufficient to establish robust stress compensation process  Leti want to be well positioned for producing ATLAS chips (1000 wafers)  Leti is proposing a complementary contract for stress compensation process based on it’s own measurement and methodology

© CEA. All rights reserved LETI proposal | 23 Papers already published Warpage Control of Silicon Interposer for 2.5D Package Application Kei Murayama1, Mitsuhiro Aizawa1, Koji Hara1, Masahiro Sunohara1, Ken Miyairi1, Kenichi Mori1, Jean Charbonnier2, Myriam Assous2, Jean-Philippe Bally2, Gilles Simon2 and Mitsutoshi Higashi1 1 SHINKO ELECTRIC INDUSTRIES CO., LTD. 2 CEA, Leti

© CEA. All rights reserved LETI proposal | 24 Protocole for stress compensation at Leti  Objective : maximum bow < 20 µm of interposer die between 20 and 260°C  Basic characterization of thin film material:  CTE measurement vs temperature with RX diffraction (high sensitivity and accuracy method)  Young modulus extraction with nano-indention method  Work at wafer level: measurement and modeling of bow evolution with temperature with stacked deposition layers  Work at die level (20x20 mm to 30x30 mm): Topography and Deformation Measurement (TDM) to vaildate the behavior of die bow with temperature Mesure de CTE=f(T°C) TDM of polymer layer on 80 µm Si interposer Modeling vs experiment of

© CEA. All rights reserved LETI proposal | 25 RUN4&5  Waiting 4 remaining wafers from GU  planning will be shifted accordingly

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