1. Micro-cooling devices for LHCb Velo CERN
LETI3S C. Charrier - C. Castellana - D. Renaud - E. Rouchouze - JF Teissier
Meeting 8 Décembre 2016

2. Short Loop 1 : Metallisation
Introduction - Layout
Short Loop 1 : Metallisation
Short Loop 2 : Dicing
Short Loop 3 : Bonding
Planning
CONFIDENTIEL
LETI 3S CERN D16F septembre 2016
CONFIDENTIEL HH

3. LAYOUT
f1 met
f1 trou
C Side
b1 flui
b1 can
b2 rep
b2 dec
N Side

4. SHORT LOOP METAL (D16S2506) : PHASE 1A
Base Wafers 550µm
Splits
P01
P02
P03
P04
P05
P06
Ti50Ni350Au500 X
Ti200Ni350Au500
Stripping 1 Fotopur
Stripping 2 EKC
F1MET05B Mask
P01 P02 P03 P05 P06
Delivered 8th of December 2016

5. SHORT LOOP DICING (D16S2225) : PHASE 1B
PLAN A : LASER DICING
240µm
260 µm
B2REP (and B2DEC dxf)
Wafers preparation :
- Initial bulk wafers 725µm
- Thermal oxidation and bonding
- Grinding front and back sides
- Photo and Silicon dry etch B2REP
MicroJet® - Synova
Feasibility : validated on W46
P01 P02 ready to be diced.
Plan : W51

6. SHORT LOOP DICING : PHASE 1B
PLASMA DICING PLAN B
240µm
260 µm
Wafers preparation (in progress) :
- Initial bulk wafers 725µm
- Thermal oxidation and bonding
- Grinding front and back sides
Photo and Silicon dry etch B2REP
Laser mark
Photo Plasma Dicing: mask to discuss
B2REP AND SPECIFIC MASK TO BE DONE
Strategy plasma Dicing OPTION 1
Red areas represent non device related surfaces to be covered with mask White lanes represent 100µm exposed Silicon channels (dicing lanes) 100µm channels should not require tape expansion to extract diced pieces
Plan : W05/2017

7. Overall masking & Street strategy Option #2
Strategy plasma Dicing OPTION 2
Red areas represent non device related surfaces to be covered with mask
White lanes represent 100µm exposed Silicon channels (dicing lanes)
Dummy die dicing channels are created to allow expansion for easy die pick
This option present a risk for localized load (higher etch rate) which might result in unbalanced etch rate between outer area and main die / wafer center)

8. Detailed view - Test structures blocks
100µm channels maintained constant in all areas

9. SHORT LOOP BONDING (D16S2603) : PHASE 1C
Base Wafers 550µm
B1FLUID and B1CAN masks
20 Wafers Bottom Si bulk 550µm
Silicon channels and capillary etching (Fluid)
20 Wafers TOP Si bulk 550µm
Wafer Lot in progress
Planning : W

10. STEP 17/47 – P2 DELIVERY W04 SHORT LOOP BONDING (D16S2603) : PHASE 1C
PLANNING
STEP 17/47 – P2
DELIVERY W04

11. Micro-cooling devices for LHCb : Current status
PLANNING - estimation
Micro-cooling devices for LHCb : Current status
T0 : GDS W40 (received on October 6th 2016) : OK
Final check : 11/09/2016
Appro MASK : W47
Delivered to LETI 11/21/2016
PHASE 1A : Metal short loop W49
Wafers delivered to CERN 12/08/2016
PHASE 1B: Grinding Dicing W51 or W05
B plan : Patterning dicing street (plasma dicing), will involve an additional mask
Laser Dicing : Wafers Ready. Delay Time for dicing 1,5 W
goal : cleanliness, chipping, wafer/device integrity, alignment accuracy
PHASE 1C: Bonding validation W02 W03
Full flow > bonding
plan: W04/2017

12. Micro-cooling devices for LHCb Velo upgrade
Initial plan V1
juil.-16
août-16
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janv.-17
févr.-17
mars-17
avr.-17
mai-17
juin-17
juil.-17
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sept.-17
oct.-17
nov.-17
déc.-17
janv.-18
févr.-18
PHASE 1
masks 1A 1B
1C*
valid CERN
PHASE 2
PF LOT
PHASE 3
LOT 1
LOT 2
LOT 3
LOT 4
LOT 5
LOT 6
LOT 7
LOT 8
simplified version

13. Micro-cooling devices for LHCb Velo upgrade
Revised 12/08/2016 V1
oct.-16
nov.-16
déc.-16
janv.-17
févr.-17
mars-17
avr.-17
mai-17
juin-17
juil.-17
août-17
sept.-17
oct.-17
nov.-17
déc.-17
janv.-18
févr.-18
mar.-18
apr.-18
may.-18
PHASE 1
masks
1A metal
1B découpe laser
1C*
valid CERN
PHASE 2
PF LOT
PHASE 3
LOT 1
LOT 2
LOT 3
LOT 4
simplified version