ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Interconnect Working Group 2008 Edition 9 December 2008 Seoul Republic of Korea Christopher Case (The Linde Group), Osamu Yamazaki (Sharp), Larry Smith (SEMATECH), Jaeyoung Yang (Dongbu HiTek), Noh Jung Kwak (Hynix), Hyeondeok Lee (Samsung), Gilheyun Choi (Samsung), Scott List (SRC)

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Japan Hideki Shibata Nobuo Aoi Taiwan Douglas CH Yu US Christopher Case Europe Hans-Joachim Barth Alexis Farcy Korea Hyeondeok Lee Sibum Kim ITWG Regional Chairs

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Partial List of Contributors Robert Geffken Hans-Joachim Barth Alexis Farcy Harold Hosack Paul Feeney Rick Reidy Mauro Kobrinsky Hideki Shibata Kazuyoshi Ueno Michele Stucchi Eiichi Nishimura Robin Cheung Didier Louis Katsuhiko Tokushige Masayoshi Imai JD Luttmer Morihiro Kada Akira Ouchi Greg Smith Detlef Weber Thomas Toms Anderson Liu Scott List Osamu Yamazaki Nobuo Aoi Scott Pozder Koji Ban Masayuki Hiroi Manabu Tsujimura Nohjung Kwak Hyeon Deok Lee Sibum Kim Lucile Arnaud Sitaram Arkalgud Azad Naeemi Dirk Gravesteijn NS Nagaraj Mike Mills Yuichi Nakao Larry Smith Skip Berry Yasushi Igarashi Gunther Schindler Chung-Liang Chang Tomoji Nakamura Shuhei Amakawa Eric Beyne Christopher Case

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Agenda Scope and structure Technology requirements Difficult challenges Energy and performance Low roadmap Interconnect for memory –DRAM wiring roadmap –Non-volatile interconnect requirements Beyond metal/dielectric systems –3D, optical and carbon nanotubes (CNT) High Density TSV Technology 2009 Preview Last words

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Interconnect scope Conductors and dielectrics –Starts at contact –Metal 1 through global levels –Includes the pre-metal dielectric (PMD) Associated planarization Necessary etch, strip and cleans Embedded passives Reliability and system and performance issues Ends at the top wiring bond pads Needs based replaced by – scaled, equivalently scaled or functional diversity drivers

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Technology Requirements Now restated and organized as –General requirements Resistivity Dielectric constant Metal levels Reliability metrics –Level specific requirements (M1, intermediate, global) Geometrical –Via size and aspect ratio –Barrier/cladding thickness –Planarization specs Materials requirements –Conductor effective resistivity and scattering effects Electrical characteristics –Delay, capacitance, crosstalk, power index

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Technology Drivers Expanding Scaled solutions –Traditional geometric scaling –Cost –necessary to enable transistor scaling). –Performance dielectric constant scaling for delay, and power improvements. –Reliability EM crosstalk Functional diversity –Increasing value by adding functionality using CMOS-compatible solutions: 3D, optical components, sensors. Contributing to More than Moore

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Difficult challenges (1 of 3) Meeting the requirements of scaled metal/dielectric systems –Managing RC delay and power New dielectrics (including air gap) Controlling conductivity (liners and scattering) –Filling small features Liners Conductor deposition –Reliability Electrical and thermo-mechanical Engineering a manufacturable interconnect stack compatible with new materials and processes –Defects –Metrology –Variability

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Difficult challenges (2 of 3) Meeting the requirements with equivalent scaling –Interconnect design and architecture (includes multi-core benefits) –Alternative metal/dielectric assemblies 3D with TSV –Interconnects beyond metal/dielectrics 3D Optical wiring CNT/Graphene –Reliability Electrical and thermo-mechanical Engineering a CMOS-compatible manufacturable interconnect system –Non-traditional materials (for optical, CNT etc.) –Unique metrology (alignment, chirality measurements, turning radius etc)

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Difficult challenges (3 of 3) Adding functional diversity –Intelligent Interconnect Active devices embedded in the interconnect BEOL Mixed technologies Si, GaAs, HgCdTe together –Mixed signalling approaches RF and analog Passive devices Repeaters in interconnect, combined metallic/semiconducting CNT interconnects Back-end memory Variable resistor via –Reliability Electrical and thermo-mechanical Engineering a CMOS-compatible manufacturable interconnect system –Non-traditional materials III/V, II/VI –Deposition (low temperature epi) –Unique metrology (composition)

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Dynamic Power Increasing concern about rising dynamic power in the interconnect stack –Interconnects make a significant contribution to total dynamic power Impacts effective k roadmap –Drives reduction in parasitic capacitance Dynamic power is a key constraint for high performance MPUs Alternative interconnect technologies (optical, CNT, RF, etc.) should be performance competitive in terms of delay and power Influence of number of functions (N), activity (A) and frequency (F): P = (NAF)CV 2

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Table INTC2 (MPU and ASIC Interconnect Technology RequirementsNear-term Years) M1_half_pitch Power index (W/GHz-cm 2 ) [x] Power index = C V dd 2 a (1 GHz) e w (1 cm 2 )/p; p = pitch; V dd = supply voltage; e w = wiring efficiency = 1/3; a = activity factor = The calculated values are an approximation for the power per GHz per cm 2 of metallization layer. This index scales with the critical parameters that determine the interconnect dynamic power. NOTES: the values provided are an average for M1, Intermediate and Global interconnects. The range of values results from the maximum and minimum effective dielectric constants.

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Effective Dielectric Constant; keff Year of 1st Shipment ITRS1999 ITRS2001 ITRS2005 ITRS ITRS2003 Historical Transition of ITRS Low-k Roadmap

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Integration Schemes

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Low-k Trend from Conference Papers ( IITC, IEDM, VL, AMC) Slow down of low-k technology development speed and large variation of k values among device companies Slow down of low-k technology development speed and large variation of k values among device companies 90 nm 65 nm 45 nm 32nm CVD SiOC DD (k=2.9) CVD SiOC DD (k=3.0) CVD SiOC DD (k=2.75)CVD SiOC DD (k=2.45) CVD SiOC DD (k=3.0) CVD SiOC DD (k=2.7) CVD SiOC DD (k=2.9) NCS/CVD SiOC stack DD (k=2.25/2.9) NCS/NCS stack DD (k=2.25/2.25) CVD SiOC DD (k=2.9) PAr/SiOC hybrid DD (k=2.6/2.5) P-PAr/p-SiOC hybrid DD (k=2.3/2.3) CVD SiOC DD (k=2.65) CVD SiOC stack DD (k=2.6/3.0) NCS/NCS stack DD (k=2.25/2.25)? ULK-PAr/SiOC hybrid DD (k=2.0/2.0) CVD SiOC DD (k=2.55)? CVD SiOC DD (k= )? Company I I T R F T

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK 90 nm 65 nm 45 nm 32nm CVD SiOC DD (k=3.0) CVD SiOC DD (k=3.0) CVD SiOC DD (k=3.0) CVD SiOC DD (k=3.0) CVD SiOC DD (k=3.0) CVD SiOC DD (k=3.0) CVD SiOC DD (k=2.75) CVD SiOC DD (k=3.0) CVD SiOC DD (k=3.0) CVD SiOC DD (k=2.8) Actual introduction in manufacturing of low-k material is one generation delayed and a variation of bulk k range among device makers is narrowing compared with trend from conference papers Actual Low-k Trend from Introduction in Manufacturing CVD SiOC DD (k=2.8) CVD SiOC DD (k=2.4)? CVD SiOC DD (k=2.4) CVD SiOC DD (k=3.0) CVD SiOC DD (k=3.0) CVD SiOC DD (k=2.6) CVD SiOC DD (k=2.8) CVD SiOC DD (k=3.0) CVD SiOC DD (k=2.75) CVD SiOC DD (k=2.4) CVD SiOC DD (k= )? CVD SiOC DD (k=2.55)? CVD SiOC DD (k=2.4) CVD SiOC DD (k=3.0)

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Change maximum bulk k value from 2.9 to 2.8 corresponding to 45nm actual introduction in manufacturing of low-k material. Beyond 2009, decrease maximum bulk k value by 0.1. ITRS2008 Low-k Roadmap Update

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK 2008 Low k update For those who think changes in k of 0.1 are significant – we aim to please For those who dont – try reaching consensus on low k with 100 people Proliferation of air-gap approaches Values of effective k-value down to 1.7 with low crosstalk levels Localized air gaps to maintain good thermal and mechanical properties Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Interlevel metal insulator – bulk dielectric constant (κ) 2.5–2.92.5–2.82.3– – Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Interlevel metal insulator – bulk dielectric constant (κ) 1.9– – –1.8

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK 2008 Barrier/Nucleation/Resistivity ALD barrier processes and metal capping layers for Cu are lagging in introduction Resistivity increases due to scattering and impact of liners No known practical solutions Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Barrier cladding thickness Metal 1 (nm) Conductor effective resistivity (µ cm) Cu Metal Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Barrier cladding thickness Metal 1 (nm) ` Conductor effective resistivity (µ cm) Cu Metal

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK DRAM Small changes in specific via and contact resistivity Contact A/R (stacked capacitor) rises to >40 in a red challenge - associated with the 40 nm DRAM half pitch High A/R Contact Interconnect and HAC FEP – now matched Cu implemented in 2007 Latest view - low k with an effective dielectric constant of 3.1 – 3.4 pushed back 3 years to 2011 Plan to distinguish embedded, flash, and traditional DRAM along with alternative memory in the interconnect in the future (2009)

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Revised DRAM Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Number of metal layers Contact A/R – stacked capacitor Metal 1 wiring pitch (nm) * Specific contact resistance (-cm 2 ) for n+ Si 1.70E E E E E E-09 Specific contact resistance (-cm 2 ) for p+ Si 2.70E E E E E E-08 Specific via resistance (-cm 2 ) 4.00E E E E E E-10 Conductor effective resistivity (µ- cm) assumes no scattering for Cu 2.2 Interlevel metal insulator – effective dielectric constant (κ) 3.6– –3.4

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Jmax 2008 Critical points for the DC pulse current, where the minimum pitch and via-size are used for high density. Frequency plans matched with design. Currently revising two key inputs to Jmax models: critical wire lengths, load assumptions and validating technology maturity color shading -Minimum Tr width (W min.): NMOS Gate width= (ASIC Half-pitch)x 4 PMOS Gate width=(NMOS Gate-width) x 2 -Tr-width (W g ): W g =W min.x 2 -Gate capacitance (C g ) -Wiring length (L i ): IM-Pitch x 400 -Wiring capacitance (C i ): Updated k eff Current density of IM-interconnect (J max ) = f (C g *W g *N+C i ) *V dd /(W i *T i ) Current density of IM-interconnect (J max ) = f (C g *W g *N+C i ) *V dd /(W i *T i ) Inverter circuit (F.O=4) C g *W g I max V dd Fan out N=4 C g *W g Intermediate wire CiCi Critical point

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK J max 2008 J max 2007 Small changes from 2007 J max values J max Update

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Emerging Interconnect (1/2) Use geometry –3D –Air gap Use different signaling methods –Signal design –Signal coding techniques Use innovative design and package options –Interconnect - centric design –Package intermediated interconnect –Chip-package co-design Figure From Stanford

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Emerging interconnect (2/2) Use different physics –Optics (waveguides, emitters, detectors, free space, trans-impedance amps, modulators) –RF/microwaves (transmitters, receivers, free space, waveguides) –Terahertz photonics Radical solutions –Nanowires/nanotubes/graphene –Molecules –Spintronics –Quantum wave functions

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK From low- to no - air gaps Introduction of air gap architectures –Creation of air gaps with non-conformal deposition –Removal of sacrificial materials after multi-level interconnects Values of effective k-value down to 1.7 with low crosstalk levels Localized air gaps to maintain good thermal and mechanical properties Ultra-low and Air gap ( <1.7) (CVD and Spin-on)

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Hypothetical On-die Optical Interconnects with WDM Wavelength specific modulator Waveguide s2 s1 s4 s2 s6 s4 … Intel Technology Journal, Volume 8, Issue 2, 2004 s1 s2 s3 s4 s5 s6

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK High Density TSV Roadmap or enabling terabits/sec at femtojoules The Interconnect perspective - examples: –High bandwidth/low energy interfaces between memory and logic –Heterogeneous integration with minimal parasitics (analog/digital, mixed substrate materials, etc.) –Re-architect chip by placing macros (functional units) on multiple tiers (wafers) and connect using HD TSVs Model assumptions: –TSV diameter limited by silicon thickness and TSV Aspect Ratio: –Pitch limited by TSV diameter, misalignment tolerance, minimum pad spacing

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK High Density TSV Technology

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK High Density TSV Specification Represents devices that could appear in production, using at least one approach to 3D integration –10 m Si thickness, wafer-to-wafer integration, wafers thinned after bonding

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK INTC6 High Density Through Silicon Specification HDTSV Diameter, Ø TSV (µm) [2], [3] Minimum Interlayer HDTSV Pitch (µm) [4] Minimum Layer Thickness (µm) [5]10 Bonding overlay accuracy, (3 sigma) (µm) [6] Minimum size bonding pad Ø pad =Ø TSV +2. (µm) Minimum pad spacing, S TSV (µm) [7] Minimum contact pitch, P TSV= Ø pad + S TSV (µm) [8] Table notes: [1] Table represents TSV and contact densities that can be achieved using wafer-to-wafer integration, with e.g. wafers thinned after bonding. Example applications include high bandwidth/low energy interfaces between memory and logic; heterogeneous integration (analog/digital, mixed substrate materials, etc.) with minimal parasitics; and chips with functional units split between tiers and connected using HDTSVs. Model assumptions include the TSV diameter being limited by the silicon thickness and TSV aspect ratio; and the contact pitch being limited by the TSV diameter, misaligment tolereance, and minimum pad spacing. See also Table AP7, which is an independent assessment. [2] Application-based scaling relationships are not well understood requirements; scaling has been assumed to be at half the rate of the MPU/ASIC M1 1/2 pitch. [3] This refers to the physical size of the TSV only, and does not include any additional "Keep-Out Area" (KOA) from which devices would be excluded. [4] Assumed to be twice the HDTSV diameter. [5] Si thickness is limited to avoid shifting transistor characteristics, especially for strained Si. Nominal thickness will be larger, to allow for Total Thickness Variation (TTV). It may eventually become necessary to decrease this thickness in order to decrease the TSV aspect ratio or the form factor. [6] Aligment accuracy between the die or wafers defines the achievable interconnect contact density using TSV's. Today this is one of the major hurdles for scaling the interconnect pitch of electrically isolated TSV connections. [7] The spacing between TSV contact pads is mainly lithographically defined, not directly in relation to the via diameter. [8] Assumes that the contacts are concentric with the TSVs. Contact pitch can differ from TSV pitch for various reasons, including: TSVs may be used for access to IO pads only, independent of wafer-to-wafer connections (e.g., for face-to-face integrations); multiple TSVs may connect to a single contact pad, e.g. for power/ground or redundancy; TSVs may fan out to contacts through a redistribution layer.

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Summary of Notable 2008 changes Low-k slowdown –New range for MPU/ASIC bulk and eff –DRAM eff of delayed 3 yrs to 2009 New Technology Introduction –ALD barrier processes and metal capping layers for Cu are lagging in introduction. No solutions seen for Cu resistivity rise - managed Power Metric –Capacitance per unit length decreases due to decreases of the dielectric constant. –The dynamic power is expected to increase because of the increased number of metallization layers, larger chip size and increased frequency.

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK 3DIC Definition and Coordination Work with Design to conduct an industry survey to determine 3D design requirements by application area Improve coordination with A&P Identify factors contributing to yield loss Work with Design and Test to identify issues with HD TSV Emerging Technologies Expansion Identify new options with ERM TWG More than Moore Category Standardization Work with other TWGs to define a common set of More than Moore categories 2009 Preview

ITRS 2008 Winter Conference – 9 December 2008 Seoul. ROK Last words More Moore –Must manage the power envelope –Must continue to meet requirements of scaled metal/dielectric systems while developing CMOS- compatible equivalent scaling solutions –Cu resistivity impact real but manageable –materials solutions alone cannot deliver performance - end of traditional scaling More than Moore –integrated system approach required –functional diversity enhances value –Focus on 3DIC and emerging interconnect