ITRS Design ITWG ITRS Design + System Drivers December 3, 2010 Design ITWG 1.Software, system level design productivity critical to roadmap 2. Manufacturability variability reliability resilience 3. Design cost will be contained through innovation 4. Design power must also be contained through innovation! improvements focus on Verification, SOC (vs. SIP) and AMS/RF System Drivers, and Cross-TWG improvements

ITRS Design ITWG Explore Design metrics Design Technology metrics Revised Design metrics Revised Design Technology Metrics Consumer Portable Driver Consumer Stationary, Portable Drivers Consumer Stationary, Portable, Networking Drivers More Than Moore (MTM) analysis + iNEMI Driver study System Drivers Chapter Design Chapter 2008 Revised Design Metrics DFM extension Updated Consumer Stationary, Portable, and Networking Drivers MTM extension + iNEMI + SW !! 2009 Additional Design Metrics DFM Extension System level extension Updated Consumer Stationary, Portable architecture, and Networking Drivers MTM extension + iNEMI synch + SW !! Overview (2004-Today) 1. Increasingly quantitative roadmap 2. Increasingly complete driver set MTM RF+AMS Driver Updated Consumer SOC and MPU Drivers Upgraded RF+AMS section 2010

ITRS Design ITWG Design / System Drivers 2010 * * Plans 1.Design chapter Improve design productivity and cost models * Develop Design Power Chart similar to Design Cost Chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for Reliability * Overhaul of Verification *, Logic/Circuit/Physical sections * 2.System Drivers chapter Flatten MPU frequency roadmap, evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * 3.Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue key interactions: A&P, Interconnect, Test * Gather input from 2 nd EDA Roadmap Workshop *

ITRS Design ITWG Todays Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

ITRS Design ITWG IC Implementation Tool Set RTL Functional Verif. Tool Suite Transaction Level Modeling Very Large Block Reuse SMP Parallel Processing Intelligent Testbench Many Core Devel. Tools AMP Parallel ProcessingExecutable Specification Silicon Virtual Prototype System Design Automation Software Virtual Prototype Concurrent Memory Figure DESN1 -- Impact of Design Technology on SoC SOC Consumer Portable Implementation Cost 2010 Updated Charts Design Productivity and COST

ITRS Design ITWG Updated Charts SOC-CP Complexity

ITRS Design ITWG Updated Charts SOC-CP Power

ITRS Design ITWG Updated Charts SOC-CP Performance

ITRS Design ITWG Figure SYSD Updated Charts SOC-CS Number of Cores and Performance

ITRS Design ITWG Figure SYSD Updated Charts SOC-CS Number of DPEs and Performance

ITRS Design ITWG Figure SYSD Updated Charts SOC-Stationary Power

ITRS Design ITWG Todays Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

ITRS Design ITWG YEAR $ SOFTWARE HARDWARE Design Cost : Design Cost Roadmap

ITRS Design ITWG : Design Cost Roadmap YEAR $ SOFTWARE HARDWARE Design Cost IC Implementation Tool Set RTL Functional Verif. Tool Suite Transaction Level Modeling Very large block reuse AMP Parallel Processing Intelligent Testbench Many Core Devel. ToolsSMP Parallel Processing Executable Specification Transactional Memory System Design Automation Design Productivity INNOVATIONS

ITRS Design ITWG : Design Power Management Roadmap ESTIMATION GATING DVFS MULTI-VDD MULTI-VT,CD GALS/ASYNC 3D / TSV RESILIENCE BTWC POWER DIST ENERGY-PROP SIGNOFF HW ACCEL

ITRS Design ITWG Basis for quantifying ITRS Grand Challenges –Productivity Power –2003: Low-Power SOC proposal –2005: Consumer Portable SOC power analysis –2006: Consumer Stationary SOC power analysis –2007: Productivity impact of low-power design –2008/9: Changes to devices, densities 2010+: Roadmap challenges increasingly organized around Power instead of Productivity –Future update of SOC Driver will comprehend heterogeneity, power management, applications, memory and communication architectures Core Effort: STRJ-WG1 SOC Modeling

ITRS Design ITWG Todays Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

ITRS Design ITWG Key Challenges in Digital Verification 18 Verification Strategy Planning Specification Design Verification Execution Optimized verification planning Develop expert human resource Definite specification without misunderstanding Exhaustive extraction of to-be-verified items, and optimized verification process IP model preparation and quality verification High-speed simulation Efficient debugging Equivalence check for C to RTL STRJ WG1 study in 2010 –Scope: HW functional verification (functional spec through RTL), high-level performance verification 8 Key Problems identified –Structure: Status, Problem, Challenges, Near-/Long-Term Solutions

ITRS Design ITWG Current Status 2010 Few engineers can develop UVM verification environment Many engineers can use assertions for dynamic simulation, but formal verification is too difficult for most engineers Training of verification engineers is local, not methodical Problem Statement Need new skills for new methodologies such as formal verification Few engineers can handle many kinds of verification methodologies Challenges Scarcity of skilled verification engineers increasing TAT and declining design quality Near-Term Solutions Implement human resources program for verification, e.g., promoting a guideline for IP verification Long-Term Solutions System for developing verification engineers, understanding how different kinds of skills are learned, and how to measure skills 19 Example: Develop Expert Human Resource

ITRS Design ITWG Current Status No IP guarantee quality 2.Must add testbench if not sufficiently provided by IP vendor 3.Both black-box and white-box IP distributed Problem Statement 1.No system that can guarantee quality of IP 2.No standard for IP models; each IP vendor has different deliverables 3.Difficult to check quality of black-box IP Challenges 1.Cannot measure quality of IP and deliverables without common quality criteria 2.Cost and time to develop additional functional models or testbenches 3.Product teams extremely nervous about quality Near-Term Solutions 1.Internal IP design review 2.Internal IP quality checks 3.Make unused functions explicit Long-Term Solutions 1.Institutionalize certification of standards-compliant IP quality 2.Guideline for IP deliverables (files/contents, must/should/could) Example: Vendor IP Model Preparation and Quality Verification

ITRS Design ITWG Current Status 2010 –Assertions and formal verification are used –Schematic viewer type debug tools are popular and widely applied. Lint type tools produce many pseudo-errors. steady human effort is of fundamental importance Problem Statement –Assertion methods not widespread because designers are unfamiliar with methods –Prioritizing extracted errors and how to resolve depends on skill of verification engineer Challenges –Efficiency in debugging is not improved –Efficiency and quality of debugging varies widely depending on engineers skills Near-Term Solutions –Automated assertion tool and support by EDA vendors –Compilation of know-how for debugging, and sharing to designers through training Long-Term Solutions –Reusable assertions as verification IP ( know-how can be applied by automated tools) –Verification IP and Verification Bench must be reusable faster setup of verification environment, greater debug efficiency 21 Example: Efficient Debugging

ITRS Design ITWG Todays Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

ITRS Design ITWG Design and System Drivers ITRS-iNEMI Domain Space Chip levelSystem level Tech requirements Market requirements iNEMI (emulators) ITRS (Drivers)

ITRS Design ITWG A&D Network Consumer Portable Office Medical Automotive Consumer Stationary MPU PE/DSP AMS Memory Fabrics Markets ? SIP New System Drivers? At the right pace… Is SIP a new fabric ? What application is the right driver for (leading edge) 3D/TSVs ? 2010? ?

ITRS Design ITWG ITRS-iNEMI Domain Space SiP-SoC More-than-Moore Proposal Chip levelSystem level Tech requirements Market requirements Portable emulator RF/AMS Driver Portable consumer driver 123 Update portable driver Update portable emulator PA Case Study (SoC v. SiP)

ITRS Design ITWG ITRS-iNEMI MTM SOC/SIP Design/Integration Update of ITRS and iNEMI Portable Drivers Inclusion of AMS/RF sub-driver from ITRS AMS driver Equivalent cost = NRE + non-NRE per-board cost 26 Other AMS PA (RF) Power (SiP) Power (SoC) Equivalent cost (SoC) Equivalent cost (SiP) PA Case Study

ITRS Design ITWG An Alternative Driver Tuner / Demodulator Inclusion of AMS/RF sub-driver from ITRS AMS driver Equivalent cost = NRE + non-NRE per-board cost 27 Power (SiP) Power (SoC) Equivalent cost (SoC) Equivalent cost (SiP) Tuner-demod case Study RequirementDescription TunerResolution, operating freqs, power ADC/DAC#bits, order, power, etc. Demodulator /FEC decoder Gain-bandwidth, power Additional rows for combined analog-digital model

ITRS Design ITWG Todays Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity – MPU Frequency Scaling Outreach

ITRS Design ITWG Power-Constrained MPU Frequency 2007: power limit led to 8%/year MPU frequency scaling, BELOW 13%/year intrinsic device CV/I scaling 2010: 8%/year too aggressive, given markets and devices 2011 Revision 2009 ITRS +8%/yr frequency -5%/yr switching +0%/yr frequency -5%/yr switching +4%/yr frequency -5%/yr switching +0%/yr frequency +0%/yr switching

ITRS Design ITWG Example Impact: Design-PIDS Cross-TWG Device speed headroom enables power savings in Design What selection of devices can PIDS provide together in a process? –High Performance (HP): Highest Ion and Ioff, lowest CV/I –Low Operating Power (LOP): Lowest VDD, medium Ion, Ioff and CV/I –Low Standby Power (LSTP): Lowest leakage, low Ion, high CV/I What ratio of device characteristics does Design want? –Preferred order of dynamic power: LOP < LSTP << HP –Preferred order of leakage power: LSTP < LOP << HP Ratio of HP : LOP : LSTP SPEED P_DYNAMIC P_STATIC Parameters Target design freq.(GHz) Device CV/I Device Ioff Application- and Market-drivenTechnology-driven Design PIDS

ITRS Design ITWG Todays Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

ITRS Design ITWG Gaps in EDA (IEEE DAC Roadmap Workshop 2010) 32 Technology EDA nature Metrics

ITRS Design ITWG THE ITRS ROADMAP ORTCs Litho PIDS FEP MTM ERD, ERM, ERA Markets Interconnect A&P Applications M&S ESH FI Metrology Test RF/AMS YE Systems Products

ITRS Design ITWG Design and System Drivers Europe: Ralf Brederlow, Wolfgang Ecker, Eric Flamand, Frederic Lalanne, Alfonso Maurelli, Wolfgang Rosenstiel, Jean-Pierre Schoellkopf, Peter Van Staa, Maarten Vertregt Japan: Yoshimi Asada, Kenji Asai, Tamotsu Hiwatashi, Koichiro Ishibashi, Masaru Kakimoto, Haruhisa Kashiwagi, Masami Matsuzaki, Kazuya Morii, Mamoru Mukuno, Katsutoshi Nakayama, Nobuto Ono, Toshitada Saito, Hiroshi Shibuya, Mikio Sumitani, Hiroki Tomoshige, Tadao Toyoda, Ichiro Yamamoto Korea: Chanseok Hwang, Chang Kim, Min Hwahn Kim USA: Fawzi Behmann, Valeria Bertacco, Yu Cao, Juan-Antonio Carballo, John Darringer, Dale Edwards, Praveen Elakkumanan, Kwangok Jeong, Bill Joyner, Andrew Kahng, Vinod Kathail, Victor Kravets, Austin Lesea, Sung Kyu Lim, Vinod Malhotra, Prasad Mantri, Grant Martin, Nikil Mehta, Sani Nassif, Bernie New, David Pan, Shishpal Rawat, Kambiz Samadi, Gary Smith, Leon Stok, Alfred Wong, David Yeh Thank You!