1 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication P. Zeitzoff Contributors: J. Hutchby, P. Fang, G. Bourianoff, J. Chung, Y. Hokari, J. Bruines, S. C. Sun, H. Bennett, T. Dellin, D. G. Kang, K. Shibahara, M. Yoshimi International Technology Working Group Meeting San Francisco, CA 7/16-7/18/01 PIDS Presentation at Open Meeting

2 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Outline Definition of PIDS Logic: high performance Logic: low power Difficult challenges Emerging research devices Summary –Reliability, Memory, and Mixed Signal here only: time constraints

3 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication PIDS Definition & Scope PIDS = Process Integration, Devices, and Structures Deals with –Full process flows and process integration –Design and optimization of active and passive devices for electrical performance –Reliability –Physical and electrical design rules Interacts with all TWGs, especially: –FEP –Interconnect –Design –Litho Main subsections: logic and memory, mixed signal, reliability, and emerging research devices (new in 2000)

4 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication High Performance Logic (MPU type) High performance logic driven by requirement of 17% annual improvement in transistor performance –Historic trend –Metric: = C gate V dd /I d –A spreadsheet used, including analytic, empirical, simplified models –Compared to 99 ITRS: scaling redone to extend viability of gate oxide, polysilicon electrode, etc. until 07 –High k and/or non-classical CMOS needed by 2007 To control short channel effects, reduce leakage, improve I on

5 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication High Performance Logic Table High k not required until 07 V dd & T ox scaling relatively slowly I off scaling up rapidly

6 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication High Performance Logic Table (cont.) 1/ improving 17%/year I d increasing slowly Needed to keep 1/ decreasing Device improvements (high mobility layers, non- classical dual gate CMOS) needed at 2007

7 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Low Power Logic Driven by requirement for reduced static and dynamic power dissipation reduced leakage Analysis is similar to high performance –Same transistor performance metric: = C gate V dd /I d –Same spreadsheet used, including analytical, empirical models Two different versions of low power –Low operating power (LOP): for notebook computers, mobile computing performance and low power: I off =I g =100 pA/µm –Low standby power (LSTP): for cellular phones super low power: I off =Ig=1 pA/µm

8 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Low Power Gate Leakage Requirements Gate leakage (A/cm 2 ) Physically effective oxide thickness (nm) 1E-10 1E-8 1E-6 1E-4 1E-2 1E 0 Pr 2 O 3 La 2 O 3 SiO 2 Al 2 O 3 ZrO 2 Ta 2 O 5 HfO Limit in LOP/ASIC Limit in MPU Limit in LSTP/ASIC 1E 2 SiON TiO 2 N/O VLSI 01

9 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Low Power [L(O)P] Requirements Table High k required in 2004 for L(O)P & L(ST)P Vdd scaling largely stops due to noise margin non- scalability There is a wall after 2007 due to high field effects inability to keep Vdd high –Performance improvement: 11%/year til 2007, flat thereafter

10 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Difficult Challenges (Short Term)

11 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Difficult Challenges (Short Term) Meeting MOSFET performance and power dissipation requirements for high performance applications. Implementation into manufacturing of non-classical MOSFET devices. Meeting MOSFET performance and leakage requirements for low power applications: high k in Ensuring reliability of new materials and structures in a timely manner. Constructing high density nonvolatile, DRAM, and SRAM memories for scaled technologies. High performance mixed signal solutions for scaled technologies.

12 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Difficult Challenges (Long Term)

13 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Difficult Challenges (Long Term) Fundamental improvements in MOSFET device effective transconductance needed to maintain device performance scaling trend. Dealing with statistical process variations and atomic-level fluctuations. New circuit and device design solutions for achieve dynamic and static low-power requirements. New interconnect schemes (optical, RF, …). Implementation of novel, non-CMOS devices and architectures, including interconnect and memory.

14 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Emerging Research Devices Devices beyond classical, bulk CMOS –Required to meet chip power dissipation and performance requirements for later technology generations Presumably, at 2007 (65nm) and beyond Includes a range of new devices and architectures –Non-classical CMOS (strained Si MOS, DG-SOI, etc.) –Advanced structures (SETs, etc.) –New information processing architectures (molecular memory, cellular neural networks, etc) –PIDS logic and memory subsection highlights need for innovative devices –Emerging Research Devices subsection expands on these devices and architectures Added to PIDS chapter in 2000, expanded in 2001

15 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication Summary Logic: Analytical, empirical models used in spreadsheet – High performance: driven by 17%/year performance improvement High k, non-classical CMOS needed by 2007 –Low power driven by power and leakage requirements High k needed in 2004; this drives introduction of high k to product Difficult challenges include implementation of high k by 2004 for low power, and in the long-term, dealing with statistical variation and atomic-level fluctuations Emerging research devices range from non-classical CMOS in 2007 to advanced, non-CMOS solutions at the end of Roadmap Memory, mixed signal, reliability only touched on due to time limitation –Key reliability issue: development and implementation time re: new materials and structures –Key memory issue: dielectric equivalent thickness, materials –Key mixed signal issue: electrical isolation