1. ASIC-LOP/LSTP Roadmap Assumptions - Vdd: 1.2V@2001, equals to the HP proposal of USA. But trend is different with each other. - Performance: 10%/year growth for LOP 5%/year growth for LSTP - Max. Ig: 100pA/um for LOP (no scaling) 1pA/um for LSTP (no scaling) - Ioff : Equals to the max. Ig of each LOP and LSTP. 16/7/2001 PIDS-Japan - Id-NMOS : 550uA/um @2001 for LOP (no scaling) 300uA/um @2001 for LSTP (no scaling)

2. Vdd in MPU(V) 1.2 1.11.00.9 0.8 Vdd in ASIC/L(O)P (V) 1.2 1.11.00.9 0.85 Maximum Ig per Tr (pA/1um) ASIC/L(O)P 100 Maximum Ig per Tr (pA/1um) ASIC/L(ST)P 1111111 Tox,eq in MPU (nm) 1.4 1.20.9 0.8 Tox,eq in ASIC/L(O)P (nm) 2.01.81.61.41.21.11.0 Tox,eq in ASIC/L(ST)P (nm) 2.62.42.22.01.81.61.4 Id-NMOS at Vdd (uA/um) ASIC/L(O)P 402421355292211224198 550572529480403427438 1.0 - High-k is put off one year, because of SiON and N/O leakage improvement Maximum Ioff at 25C (pA/um) ASIC/L(O)P 100 Maximum Ioff at 25C (pA/um) ASIC/L(ST)P 1111111 Id-NMOS at Vdd (uA/um) ASIC/L(ST)P 16/7/2001 PIDS-Japan Vdd in ASIC/L(ST)P (V) 1.2 1.1 1.0 0.9 Performance L(O)P Performance L(ST)P 1.01.11.21.31.41.51.6 1.01.1 1.2 1.3 ASIC/LOP, LSTP Roadmap

3. 0 1 2 3 Gate leakage (A/cm 2 ) Physically effective oxide thickness (nm) 1E-10 1E-8 1E-6 1E-4 1E-2 1E 0 Pr 2 O 3 La 2 O 3 SiO 2 Al 2 O 3 ZrO 2 Ta 2 O 5 HfO 2 Gate leakage current vs. insulator thickness @Vg=1V Limit in LOP/ASIC Limit in MPU Limit in LSTP/ASIC 1E 2 ITRS ’01-4-26 PIDS-Japan SiON TiO 2 N/O (Revised) VLSI ‘01