1 Adaptive On-Chip Test Strategies for Complex Systems V. Stopjaková Department of Microelectronics, STU Bratislava, Slovakia

2 Electronics Industry Trends n Achieved successful penetration in different domains n Emergence of technology Greater complexity Increased performance Higher density Lower power dissipation

3 Market-Driven Products n Meet user Quality requirements u satisfying users to buy products n Created an unprecedented Dependency  market-driven products n Maintain competitive by providing: u Greater Product Functionality u Lower Cost u Reduced Interval (time to market) u Higher Reliability

4 High Complexity: Mixed Systems n A single chip: Logic, Analog, DRAM blocks n Embed advanced blocks: u FPGA, Flash, RF/Microwave n Others u MEMS u Optical elements FPGA DRAM SRAM LOGIC FLASH RF Analog Logic LOGIC ANALOG DRAM

5 High Complexity: Mixed Systems n How to test the mixed chip? n With external test only - need multiple ATE for a single chip: Logic ATE, Memory ATE, Analog ATE (Double/Triple Insertion) n Need special ATE with combined capabilities

6 High Complexity: External Test n External Test Data Volume can be extremely high (function of chip complexity) n Requires deep tester memory for scan I/O pins n Slow test with long scan chains External Test Super ATE Pattern Generation Precision Timing Diagnostics Power Management Test Control Very high pin count Deep memory Slow serial SCAN Logic Mixed- Signal Memory I/Os & Interconnects Source: LogicVision

7 High Complexity: On-chip Test n Solution: Dedicated Built-In Test for embedded blocks n Tasks repartitioned into embedded test and external test functions External Test Standard Digital Tester Limited Speed/ Accuracy On-chip Test Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test Logic Mixed- Signal Memory I/Os & Interconnects Chip, Board or System Source: LogicVision

8 Technology motivation n many CMOS defects escaping logic testing n physical imperfections causing delay faults n unmodeled faults (weak-1, weak-0) Quality & Reliability of IC affected ! n Conventional test methods not effective New on-chip test methods have to be applied

9 Supply Current Testing I DD t faulty I DDQ I DDT fault-free NMOS defect PMOS V DD I outin Figure 1 Principle of the supply current testing PASS/FAIL reference

10 IDDQ/T testing - realization n Off-chip measurement by external equipment n On-chip monitoring using Built-In Current (BIC) monitors Off-chip monitors: + no additional chip area needed - slow measurement (decoupling capacitor) - small current masked by noise BIC Monitors: +sensitive, very fast and accurate +applicable in on-chip methods - chip area overhead -CUT perturbation

11 IDDQ testing crucial issues n Pass/Fail limit setting u represents fault-free value of IDDQ current u depends on number of factors: technology, type of circuits,... u if too high - defective circuits pass u if too low - undesired yield decrease (false fault detections) n Test vectors n Measurement Hardware

12 On-chip IDDQ Monitoring Principle DUT I DD G ND V DD G ND ’ Pass/Fail + - Vref BICM Sensing element Figure 2 On-chip supply current testing

13 Main requirements for on-chip current monitors u ability to sense high currents u testing of low-voltage circuits u a minimal number of extra pins u design simplicity u applicable for recent VLSI circuits Monitor development focused on: u effect on performance of the CUT u area overhead u testing speed u accuracy and sensitivity

14 Example of a quiescent on-chip monitor based on CCII+ current conveyor n I DD current measurement  current comparison  I DDQ sampling Figure 3 Current conveyor based quiescent BIC monitor

15 BIC monitor layout Figure 4 The core of the monitor layout  size of 1  bypass switch is 650  m x 210  m (80%)  total area of 0.22 mm 2

16 Evaluation results n resolution of 10nA n Pass/Fail limit of 50nA (sensitivity) n 1 MHz testing speed n VDD degradation max.100mV n area overhead of 0.22 mm 2 n ability to handle large CMOS IC

17 Useful for Differential Analog Test Figure 5 Experimental BIC monitor usage in a new ABIST approach

18 Current mirror IDD principle Figure 6 Current mirror principle of I DD monitoring

19 Example of a transient on-chip monitor Figure 7 Transient BIC monitor CUT I MIR I DD M S C D V ref V mon Test V offset V DD V DD’ Current Mirror BIC monitor A

20 Experimental digital chip n both BIC monitors integrated in BIC-MU n BIC-MU implemented into a digital circuit n a digital multiplier used as a CUT n fabricated in 0.7  m CMOS n multiplier size 850  m  850  m n area of BIC-MU is 0.24mm 2 n around 24% of the total chip area

21 Figure 8 Layout of the experimental chip

22 Versatility Problem of IDD Testing n I DD testing proven very successful for digital circuits n Dedicated fault class only n Use in submicron technologies limited n I DD testing for analog IC not straightforward F Large variety of analog IC F Specifications and behavior unique F Difficult to generalize analog tests F Validation up to now done using functional criteria Current consumption analysis using Neural Networks

23 Artificial Neural Networks Approach n Current signature analysis for presence of abnormal (faulty) behavior n Massively parallel and distributed structures capable of adaptation n No explicit Pass/Fail limit formulation required n Excellent versatility n Accuracy and sensitivity n Reduced number of TP (time to test)

24 I DD analysis using ANN I DD time or freq 1, 0 0, 1 (GOOD) (BAD) Figure 9 ANN-based analysis of I DD

25 Mathematical model xPxP bkbk x1x1 w k1 w kP  (u k ) ukuk ykyk Figure 10 Mathematical model of an artificial neuron

26 Activation function Figure 11 Activation function with top and bottom decision levels

27 ANN Classification of tested ICs n ANN with two outputs: n1, n2 n Classification within top/bottom decision levels n1  TDL & n2  BDL  PASS n1  BDL & n2  TDL  FAIL Otherwise  Non Classified

28 Analog DUT Example n Two-stage CMOS operational amplifier n A pulse used as input stimuli n Good patterns: technology parameters and temperature variations n Faulty behavior: basic defects injected (GOS, DOP, SOP, DSS, GSS, GDS)

29 Effect of the GOS Fault Figure 12 Effect of the GOS faults on I DD signal in time and frequency domain

30 Effect of the DSS Fault Figure 13 Effect of the DSS fault on I DD signal in different domains

31 ANN setup n 660 tested power supply current waveforms n 200 faulty patterns n 460 fault-free patterns n 32 input nodes n various training set: 200, 100, 76, 50 and 26 n various number of hidden units: 2, 6, 10, 14, 18, 22 n top decision level: 0.9 n bottom decision level: 0.1 n 10 independent measurements

32 Classification results Figure 14 Percent Correct Classification (PCC) for time domain

33 Classification results(2) Figure 15 Percent Correct Classification for frequency domain

34 Conclusions n To ensure quality of SoC Technologies: u On-chip Test is added into the designs of embedded cores n New adaptive on-chip approaches needed for different test functions n On-chip current monitoring effective but not versatile and limited to CMOS digital circuit n ANN classification of defective IC u ability of testing mixed-signal circuits u ability of sensing negligible differences u possibility to analyse other circuit’s parameters

35 Thank YOU for your attention!