ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan 1 PIDS Update December 3, 2010 Makuhari, Japan PIDS Members Speaker: Kwok Ng (U.S. Chair)

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan 2 C=Chair, CC=Co-Chair, VC=Vice-Chair PIDS Roster US Ng, Kwok C Antoniadis, Dimitri Bhavnagarwala,Azeez Brewer, Joe Bersuker, Gennadi Chang, Chorng-Ping Cheung, Kin (Charles) Dellin, Ted Henderson, Christopher Hutchby, Jim Krishnan, Shrikanth Lam, Chung Maszara, Witek Ning, Tak Prall, Kirk Stathis, James Tsai, Wilman Wong, Philip Xiang, Qi Yeap, Geoffrey Yu, Scott Zeitzoff, Peter Japan Matsuo, Ichiro C Inoue, Hirofumi VC Akasaka, Yasushi Hiramoto, Toshiro Hisamoto, Digh Hori, Atsushi Ida, Jiro Iwamoro, Kunihiko Kiyota, Yukihiro Kurata, Hajime Mogami, Tohru Oda, Hidekazu Shibahara, Kentaro Sugii, Toshihiro Takagi, Shinichi Tanaka, Tetsu Wakabayashi, Hitoshi Yoshimi, Makoro Europe Skotnicki, Thomas C Boeuf, Frederic Burenkov, Alex DeMeyer, Kristin Jurczak, Malgorzata Kuper, Fred Lander, Robert Poiroux, Thierry Schulz, Thomas Taiwan Liu, Rich CC Tsai, Cheng-tzung CC Diaz, Carlos Oates, Tony See, Yee-Chaung Korea Cha, Seon Yong Jin, Gyoyoung Jeong, Moon-Young Park, Jongwoo

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan 3 Outline PIDS Mission and Technical Sub-Groups o Logic o Memory: DRAM o Memory: Nonvolatile o Reliability 2010 Edition Update Summary Plans for 2011 Edition

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan 4 PIDS = Process Integration, Devices, & Structures Mission: o Provide physical and electrical requirements and solutions for sustaining IC scaling in digital logic technologies and memory technologies. o Scopes: Performance (speed, density, power, functionality…) Structures Process-integration challenges Reliability

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan 5 PIDS Technical Sub-Groups Logic (Leads = Kwok Ng, Ichiro Matsuo) o HP = High Performance (e.g., P…) o LOP = Low Operating (Dynamic) Power (e.g., notebook…) o LSTP = Low Standby (Static) Power (e.g., cellular…) Memory: DRAM(Lead = Hirofumi Inoue) Memory: Nonvolatile(Leads = Rich Liu, Hirofumi Inoue) Reliability (Lead = Charles Cheung) Speed (I/CV)Static Power (I off )Dynamic Power (CV 2 ) HPRef LOPLow Lowest LSTPLowest Low

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan Update: Logic Low Operating Power (LOP) Technology Requirements o Power supply voltages V dd lowered to reduce the dynamic power. o From this change, the speed I/CV values are reduced by amounts ranging 14–34% from those of These speeds are considered adequate. Low Standby Power (LSTP) Technology Requirements: o Off-current I off reduced from 50 pA/ m to 10 pA/ m to decrease the static power. o Power supply voltages V dd lowered to similar values as those of HP technology to reduce the dynamic power. o From these changes, the speed I/CV values are reduced by the amounts ranging 20–57% from those of These speeds are considered to be adequate for their functions.

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan Update: DRAM Survey had been performed by Japan PIDS. Together with market observations, following changes are made (only in PIDS chapter but not yet in ORTC and other chapters until 2011): o Half-pitch scaling is accelerated by 1 year for the next 5 years. o Structure transition from RCAT to FinFET is delayed by 2 years to o VCT (vertical channel transistor) will be launched in 2013 and continues till end of roadmap. o Cell size factor transition to 4F 2 will be delayed by 2 years. o Support PMOS gate electrode transition to TiN metal gate is delayed by 2 years.

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan Update: Nonvolatile Memory NAND flash survey had been performed by Japan PIDS. Together with market observations, following changes had been made (only in PIDS chapter but not yet in ORTC and other chapters until 2011): o Half-pitch scaling is accelerated by 1 year. o Product density (in Gb) is accelerated by 1 year. o Introduction of 3-D stacking is delayed by 1 year to o Transition to 4 bit/cell is delayed by 7 years to Update: Reliability No update.

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan 9 Plans for 2011 Edition Since the increase per year in circuit clock frequency has slowed down, on-going discussion with Design TWG and industry on device speed (I/CV) scaling requirements. (i.e., can current I/CV increase of 13%/yr be reduced?) Add dynamic power metric CV 2 on logic devices (HP, LOP, and LSTP). Revisit whether we should eliminate LOP device. Add/use commercial state-of-the-art numerical device simulator for calculating electrical characteristics to supplement MASTAR (analytical). Working closely with Modeling TWG. Planning to add III-V (for n-channel) and Ge (for p-channel) as alternate channel materials for low-V dd (low dynamic power) options, i.e., HP & LOP. Product introduction year = 2018.

ITRS Winter Meeting. Dec. 3, 2010 Makuhari, Japan 10 Plans for 2011 Edition (contd) New DRAM survey being performed by Japan PIDS, to be completed Jan/2011. NAND flash: 1-year pull in. Distinguish 3-D NAND from planar NAND with separate values in half-pitch, MLC, density... STT MRAM: Consider moving from Potential Solution to Technology Requirements table (as a main-stream technology option). Planning survey, to be completed by March/2011. (End)