Designing Combinational Logic Circuits in Verilog - 2 Discussion 7.3

Designing Combinational Logic Circuits in Verilog - 2 Binary to Gray code converter Gray code to binary converter Binary-to-BCD converter

Gray Code Definition: An ordering of 2n binary numbers such that only one bit changes from one entry to the next. Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111} Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100} Not unique One method for generating a Gray code sequence: Start with all bits zero and successively flip the right-most bit that produces a new string.

Binary - Gray Code Conversions Gray code: G[i], i = n – 1 : 0 Binary code: B[i], i = n – 1 : 0 Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111} Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100} Convert Binary to Gray: Copy the most significant bit. For each smaller i G[i] = B[i+1] ^ B[i] Convert Gray to Binary: Copy the most significant bit. For each smaller i B[i] = B[i+1] ^ G[i]

Gray Code Binary B[2:0] Gray Code G[2:0] Note that the least significant bit that can be changed without repeating a value is the bit that is changed 000 000 001 001 010 011 011 010 100 110 101 111 110 101 111 100 Binary to Gray code G[2] = B[2]; G[1:0] = B[2:1] ^ B[1:0];

Binary to Gray code grayCode = binary ^ (binary >> 1) G(msb) = B(msb); for(j = msb-1; j >= 0; j=j-1) G(j) = B(j+1) ^ B(j); msb = 5 for 6-bit codes

bin2gray.v module bin2gray ( B ,G ); input [3:0] B ; wire [3:0] B ; output [3:0] G ; wire [3:0] G ; assign G[3] = B[3]; assign G[2:0] = B[3:1] ^ B[2:0]; endmodule Convert Binary to Gray: Copy the most significant bit. For each smaller i G[i] = B[i+1] ^ B[i]

Binary to Gray Code Conversion

Designing Combinational Logic Circuits in Verilog - 2 Binary to Gray code converter Gray code to binary converter Binary-to-BCD converter

Binary - Gray Code Conversions Gray code: G[i], i = n – 1 : 0 Binary code: B[i], i = n – 1 : 0 Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111} Gray coding {0...7}: {000, 001, 011, 010, 110, 111, 101, 100} Convert Binary to Gray: Copy the most significant bit. For each smaller i G[i] = B[i+1] ^ B[i] Convert Gray to Binary: Copy the most significant bit. For each smaller i B[i] = B[i+1] ^ G[i]

Gray Code Binary B[2:0] Gray Code G[2:0] 000 000 001 001 010 011 011 010 100 110 101 111 110 101 111 100 Gray code to Binary B[2] = G[2]; B[1:0] = B[2:1] ^ G[1:0];

Gray code to Binary B(msb) = G(msb); for(j = msb-1; j >= 0; j--) B(j) = B(j+1) ^ G(j);

Gray code to Binary module gray2bin6 ( G ,B ); input [5:0] G ; wire [5:0] G ; output [5:0] B ; wire [5:0] B ; assign B[5] = G[5]; assign B[4:0] = B[5:1] ^ G[4:0]; endmodule B(msb) = G(msb); for(j = msb-1; j >= 0; j=j-1) B(j) = B(j+1) ^ G(j);

gray2bin.v module gray2bin ( G ,B ); input [3:0] G ; wire [3:0] G ; output [3:0] B ; reg [3:0] B ; integer i; always @(G) begin B[3] = G[3]; for(i=2; i >= 0; i = i-1) B[i] = B[i+1] ^ G[i]; end endmodule Convert Gray to Binary: Copy the most significant bit. For each smaller i B[i] = B[i+1] ^ G[i]

Gray Code to Binary Conversion

Designing Combinational Logic Circuits in Verilog - 2 Binary to Gray code converter Gray code to binary converter Binary-to-BCD converter

Shift and Add-3 Algorithm   S1. Shift the binary number left one bit. 22. If 8 shifts have taken place, the BCD number is in the Hundreds, Tens, and Units column. 33. If the binary value in any of the BCD columns is 5 or greater, add 3 to that value in that BCD column. 44. Go to 1.

Steps to convert an 8-bit binary number to BCD

Truth table for Add-3 Module A3 A2 A1 A0 C S3 S2 S1 S0

K-Map for S3 A1 A0 00 01 11 10 A3 A2 00 01 1 1 1 11 X X X X 10 1 1 X X S3 = A3 | A2 & A0 | A2 & A1

Binary-to-BCD Converter RTL Solution

1. Clear all bits of z to zero 2. Shift B left 3 bits z[8:3] = B[5:0]; Steps to convert a 6-bit binary number to BCD 1. Clear all bits of z to zero 2. Shift B left 3 bits z[8:3] = B[5:0]; 3. Do 3 times if Units >4 then add 3 to Units (note: Units = z[9:6]) Shift z left 1 bit 4. Tens = P[6:4] = z[12:10] Units = P[3:0] = z[9:6]

binbcd6.v module binbcd6(B,P); input [5:0] B; output [6:0] P; reg [6:0] P; reg [12:0] z; integer i; always @(B) begin for(i = 0; i <= 12; i = i+1) z[i] = 0; z[8:3] = B; for(i = 0; i <= 2; i = i+1) if(z[9:6] > 4) z[9:6] = z[9:6] + 3; z[12:1] = z[11:0]; end P = z[12:6]; endmodule

binbcd6.v

binbcd8.v module binbcd8(B,P); input [7:0] B; output [9:0] P; reg [9:0] P; reg [17:0] z; integer i; always @(B) begin for(i = 0; i <= 17; i = i+1) z[i] = 0; z[10:3] = B; for(i = 1; i <= 5; i = i+1) if(z[11:8] > 4) z[11:8] = z[11:8] + 3; if(z[15:12] > 4) z[15:12] = z[15:12] + 3; z[17:1] = z[16:0]; end P = z[17:8]; endmodule binbcd8.v

binbcd8.v

binbcd9.v module binbcd9(B,P); input [8:0] B; output [10:0] P; reg [10:0] P; reg [19:0] z; integer i; always @(B) begin for(i = 0; i <= 19; i = i+1) z[i] = 0; z[11:3] = B; for(i = 0; i <= 5; i = i+1) if(z[12:9] > 4) z[12:9] = z[12:9] + 3; if(z[16:13] > 4) z[16:13] = z[16:13] + 3; z[19:1] = z[18:0]; end P = z[19:9]; endmodule binbcd9.v

binbcd9.v

16-bit Binary-to-BCD Converter

binbcd16.v module binbcd16(B,P); input [15:0] B; output [18:0] P; reg [18:0] P; reg [31:0] z; integer i;

always @(B) begin for(i = 0; i <= 31; i = i+1) z[i] = 0; z[18:3] = B; for(i = 0; i <= 12; i = i+1) if(z[19:16] > 4) z[19:16] = z[19:16] + 3; if(z[23:20] > 4) z[23:20] = z[23:20] + 3; if(z[27:24] > 4) z[27:24] = z[27:24] + 3; if(z[31:28] > 4) z[31:28] = z[31:28] + 3; z[31:1] = z[30:0]; end P = z[31:16]; endmodule

binbcd16.v