Accuracy-Configurable Adder for Approximate Arithmetic Designs Andrew B. Kahng, Seokhyeong Kang VLSI CAD LABORATORY, UC San Diego 49th Design Automation Conference June 6th, 2012

Outline Background and Motivation Accuracy Configurable Adder Design Experimental Setup and Results Conclusions and Ongoing Works

Why Approximate Designs? Threats to traditional IC design approach ... Extreme variations: PVT variation uncertainty lead to design overhead Reliability issues: Hard errors (NBTI, latchup), Soft errors (α-particle) Cost: Cost (power/performance) of perfect accuracy is too high! Approximate designs Relaxing the requirement of correctness can dramatically reduce costs of the design Threats to traditional IC design approach ... Extreme variations / Reliability issues / Cost: Approximate designs Relaxing the requirement of correctness can dramatically reduce costs of the design What is the square root of 10 ? “a little more than three” “3.162278....” Approximation could be faster and more powerful

Previous Approximate Adders Lu et al. IEEE Computer 2004 Faster adder w/ shorter carry chain High performance with small error rate Large area overhead: not applicable for low energy design Zhu et al. TVLSI 2010 ETAI : accurate part + inaccurate part Reduce error size Error rate is high Output accuracy is fixed  benefits can be limited by required accuracy

Our Work: Accuracy-Configurable Approximate Adder How power benefits can be achieved … Accuracy-configurable design adapts to changing requirements by using different modes in each situation

Our Work: Accuracy-Configurable Approximate Adder How power benefits can be achieved … Accuracy-configurable approximate adder approximate adder error collection (ECC-1) error collection (ECC-2) accuracy: 90% accuracy: 95% accuracy: 100% Mode 1: turn-off ECC-1, ECC-2 Mode 2: turn-off ECC-2 Mode 3: turn-on All ECC

Outline Background Motivation Accuracy Configurable Adder Design Experimental Setup and Results Conclusions and Ongoing Works

Approximate Adder Implementation 16-bit adder case Carry chain is cut to reduce critical path delay Sub-adders generate results of partial summation Middle sub-adder improves accuracy (error 50%  5.5%)

Approximate Adder Implementation N-bit adder case carry Probability of correct result : Estimation over CLA (N=16) K 2 3 4 5 6 Min. clock cycle 0.5 0.65 0.75 0.83 0.89 area 0.87 1.05 1.12 1.15 power 0.44 0.68 0.84 0.95 1.00 pass rate 0.554 0.829 0.942 0.982 0.995 Approximate adder can be configured with “k”

Error Detection and Correction Variable latency operation Error can be detected and corrected with small overhead Error detection: ‘and’ gates Error correction: incrementor circuit Error detection and correction can take more time than critical path delay of “sub-adder”; the throughput can be reduced

Accuracy Configuration with Pipeline power gating power gating power gating Each stage generates a result with different accuracy Can turn off later stages with power gating according to accuracy requirement Config. Power- gating Accuracy Power reduction Mode-1 None 1.000 -11.5% Mode-2 Stage 4 0.960 12.4% Mode-3 Stage-3, 4 0.925 31.0% Mode-4 Stage-2, 3, 4 0.900 51.6%

Outline Background Motivation Accuracy Configurable Adder Design Experimental Setup and Results Conclusions and Ongoing Works

Experimental Setup and Metrics Library: TSMC 65GP Implementation: Synopsys Design Compiler Simulation: Cadence NC-SIM Input patterns: random data and actual data Library preparation: Cadence Library Characterizer Accuracy Metrics Metric Definition Data type ACCamp 1-|Rc-Re|/Rc Amplitude data ACCinf 1-Be/Bw Information data Rc and Re : correct and obtained results Be: number of error bits, Bw: bit-width of data

Approximate Adder Comparison Accuracy vs. power consumption Image smoothing (Gaussian filter) Original image Accurate adder ACA (PSNR 24.5dB) ETAI (25.3dB) ETAII (16.2dB) LU (11.1dB) (a) (b) (c) (c)~(f) have 50% power of accurate adder (b) (d) (e) (f) * ETAI cannot detect and correct errors

Approximate Adder Comparison Accuracy vs. power consumption w/voltage scaling Voltage scaling (1.0V~0.6V) ACA adder shows fine results (accuracy vs. power) on both ACCamp and ACCinf metrics

Accuracy Configuration and Power Saving Power saving from voltage scaling + mode change 4-stage 32-bit adder case accurate result Accuracy: 1.0 → 0.9 voltage scaling mode change 4X reduction voltage scaling mode change Accuracy configuration w/ mode change is more effective than w/ voltage scaling

Accuracy Configuration and Power Saving Power consumption when accuracy requirement is varying (w/ SPEC 2006 benchmarks) High accuracy Average 30% power savings over no accuracy configuration

Outline Background Motivation Accuracy Configurable Adder Design Experimental Setup and Results Conclusions and Ongoing Works

Conclusions and Ongoing Works We proposed accuracy-configurable approximate (ACA) adder, which can adapt to changing accuracy requirement ACA can provide 30% power reduction with accuracy configuration during runtime Ongoing Works Accuracy-configurable design for other arithmetic units (multiplier, divider) Automated synthesis flow (minimize power under the required accuracy) RTL Required accuracy exact adder approximate adder Synthesis Accuracy estimation

Thank You!

Accuracy-Configurable Approximate Design Required accuracy can change during runtime Idea of High-Efficiency Math highlighted by Intel Labs at ISSCC-2012 Variable-precision floating point unit w/ accuracy tracking : 24-bit  12-bit  6-bit as needed Variable-precision Mantissa Accuracy-configurable design adapts to changing requirements, maximizing benefits of approximate design paradigm The required accuracy … according to the applications. Intel Labs presented. As shown in this figure, In this work, we propose an accuracy-configurable approximate design.