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Presentation transcript:

Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 8 Memory Systems Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.1 The memory interface Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.2 Diverging processor and memory performance Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2012. Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.3 A typical memory hierarchy Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.4 Memory hierarchy components, with typical characteristics in 2012 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.5 Mapping of main memory to a direct mapped cache Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.6 Cache fields for address 0xFFFFFFE4 when mapping to the cache in Figure 8.5 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.7 Direct mapped cache with 8 sets Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.8 Direct mapped cache contents Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.9 Two-way set associative cache Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.10 Two-way set associative cache contents Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.11 Eight-block fully associative cache Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.12 Direct mapped cache with two sets and a four-word block size Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.13 Cache fields for address 0x8000009C when mapping to the cache of Figure 8.12 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.14 Cache contents with a block size b of four words Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.15 Two-way associative cache with LRU replacement Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.16 Memory hierarchy with two levels of cache Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.17 Miss rate versus cache size and associativity on SPEC2000 benchmark Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2012. Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.18 Miss rate versus block size and cache size on SPEC92 benchmark Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2012. Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.19 Hard disk Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.20 Virtual and physical pages Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.21 Physical and virtual pages Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.22 Translation from virtual address to physical address Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.23 The page table for Figure 8.21 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.24 Address translation using the page table Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.25 Address translation using a two-entry TLB Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.26 Hierarchical page tables Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.27 Address translation using a two-level page table Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.28 Support hardware for memory-mapped I/O Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.29 PIC32MX675F512H block diagram ( 2012 Microchip Technology Inc.; reprinted with permission.) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.30 PIC32 memory map ( 2012 Microchip Technology Inc.; reprinted with permission.) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.31 PIC32MX6xxFxxH pinout. Black pins are 5 V-tolerant. ( 2012 Microchip Technology Inc.; reprinted with permission.) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.32 PIC32 in 64-pin TQFP package Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.33 PIC32 basic operational schematic Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.34 Microchip ICD3 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.35 LEDs and switches connected to 12-bit GPIO port D Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.36 SPI connection and master waveforms Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.37 SPI connection between PIC32 and FPGA Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.38 SPI slave circuitry and timing Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.39 Clock and data timing controlled by CKE, CKP, and SAMPLE Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.40 Asynchronous serial link Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.41 Cap’n Crunch Bosun Whistle. Photograph by Evrim Sen, reprinted with permission. Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.42 DE-9 male cable (a) pinout, (b) standard wiring, and (c) null modem wiring Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.43 PIC32 to PC serial link Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.44 Plugable USB to RS-232 DB9 Serial Adapter ( 2012 Plugable Technologies; reprinted with permission) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.45 ADC and DAC symbols Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.46 DAC parallel and serial interfaces to a PIC32 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.47 Pulse-width modulated (PWM) signal Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.48 Analog output using PWM and low-pass filter Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.49 Crystalfontz CFAH2002A-TMI 20  2 character LCD ( 2012 Crystalfontz America; reprinted with permission.) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.50 Parallel LCD interface Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.51 VGA timing: (a) horizontal, (b) vertical Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.52 VGA connector pinout Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.53 FPGA driving VGA cable through video DAC Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.54 VGA output Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.55 FSK and GFSK waveforms Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.56 BlueSMiRF module and USB dongle Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.57 Bluetooth PIC32 to PC link Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.58 DC motor Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.59 H-bridge Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.60 Motor control with dual H-bridge Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.61 Shaft encoder (a) disk, (b) quadrature outputs Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.62 SG90 servo motor Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.63 Servo control waveform Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.64 Servo motor control Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.65 (a) Simplified bipolar stepper motor; (b) stepper motor symbol Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.66 Bipolar motor drive Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.67 AIRPAX LB82773-M1 bipolar stepper motor Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.68 Bipolar stepper motor direct drive current: (a) slow rotation, (b) fast rotation, (c) fast rotation with chopper drive Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.69 Bipolar stepper motor direct drive with H-bridge Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.70 Gigabyte GA-H55M-S2V Motherboard Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.71 DDR3 memory module Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.72 SATA cable Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.73 NI myDAQ Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.74 FTDI USB to MPSSE cable ( 2012 by FTDI; reprinted with permission.) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.75 C232HM-DDHSL USB to MPSESE interface from PC to FPGA Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.76 FTDI UM232H module ( 2012 by FTDI; reprinted with permission.) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.77 Pentium Pro multichip module with processor (left) and 256-KB cache (right) in a pin grid array (PGA) package (Courtesy Intel.) Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.78 Building blocks Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.79 Computer system Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 01 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 02 Copyright © 2013 Elsevier Inc. All rights reserved.

Copyright © 2013 Elsevier Inc. All rights reserved. UNN Figure 1 Copyright © 2013 Elsevier Inc. All rights reserved.