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New Trends in VLSI Design

Processor Performance

Why is Performance Improving? Better circuit design More memory, cache and register More parallelism (wider data bus, pipelining, etc.) Transistors are switching faster!!!!

Simple Scaling Parameter Full Scaling Constant Voltage Scaling Dimensions: width, length, oxide thickness 1/S Voltages: supply, threshold 1/S1 Intrinsic gate delay1/S1/S 2 Gate Capacitance1/S Current per device1/SS Power dissipation per gate1/S 2 S

Chip Area Technology (  m) Intel 386 DX Intel 486 DX Pentium Pentium Pro & Pentium II 1cm 2 Remark:  m = mircon

Transistor Count vs. Year

Average Transistor Price vs. Year

Can Scaling Continue in Future? Scaling works well in the past In order to keep scaling to work in the future, many technical problems need to be solved. Year Technology (  m)

The Roadmap National Technology Roadmap for Semiconductors (NTRS) Called ITRS (International TRS) since 4 th Ed Projection of future technology requirements for the next 15 years. EditionYear of Publication 1st1992 2nd1994 3rd1997 4th1999

Roadmap Overview Focus Technology Working Groups –Design & Test –Process Integration, Devices & Structures –Front End Process –Lithography –Interconnect –Factory Integration –Assembly & Packaging Crosscut Technology Working Groups –Environment, Safety & Health –Defect Reduction –Metrology –Modeling & Simulation

Technology Characteristics Year Technology (  m) Density (#trans./cm 2 ) 6.2M10M18M39M84M180M Chip size (cm 2 ) Power (W) Frequency (MHz) # routing layers *Data for high-performance microprocessor *Data from 97 Edition of Roadmap

Technical Problems with Future VLSI Technology

Too much transistors Design are too complicated No way to do it manually Solutions: –CAD –Design hierarchically –Design reuse

Area, Performance, Power, Noise Important to keep area small. How to achieve such a good performance? Power consumption is huge. Heat dissipation is also a problem. Both Capacitive and Inductive Noises are not ignorable now. Solutions: –Physical Design is an appropriate stage to handle all these. –Many research needs to be done.

Interconnect Area Too many interconnects. Occupy too much area. Solution: –More interconnect layers. –Made possible by Chemical-Mechanical Polishing (CMP). –Note that more layers doesn’t necessarily mean less interconnect area. –Also, routing is no longer a 2-D problem. Hence, new CAD algorithms needed.

SEM Photo of Metal Layers

Cross-Section of Metal Layers

19 Interconnect Delay Technology Generation(  m) Source: SIA Roadmap 97

Interconnect Delay Dominating factor in determining circuit performance nowadays. Solutions: –Copper wire –Low-k (dielectric constant) material –Interconnect Optimization at physical design

Design Planning Need to plan ahead during the early stages of VLSI design cycle. Need to take physical design into consideration early. Many research needs to be done.

Summary Technology Trend: –Transistors are smaller. –Transistors and Interconnects are denser. –Chip areas are larger. –Number of metal layers are more. Problems: –Design complexity. –Tradeoff of Area, Performance, Power, Noise. –Interconnect area and Interconnect delay. –Increasing planning requirements.