ASIC IP AND BEYOND 職場經驗分享 Sharing the Working Experience March 2005 Frank Cheng Frank Cheng 鄭順發 International Business Operations / Field Marketing Development

2 Contents  Self Introduction  Sharing in Working Experience  Job Opportunities  Open Discussion

3 Contents  Self Introduction  Sharing in Working Experience  Job Opportunities  Open Discussion

4 Self Introduction - I  Graduated from 電子資訊研究所 - 甲組 in 1996  Live in HsinChu  Married with 2 sons  Career history  1st job in SRRC 同步輻射研究中心 (1996/7-1997/7) - 1yr  2nd job in ITRI’s 量測中心 (1997/7-1999/6) - 2yrs  3rd job in AMIC 聯笙電子 (1999/6-2000/2) -.75 yr  4th job in Faraday 智原科技 (2000/2 ~ ) - 5yr

5 Self Introduction - II  SRRC 同步輻射研究中心 (1996/7~1997/7)  Division: 注射器組  Maintained the Booster ( 加速環 ) 設備  Power system  Electronic controlling system  Maintain Work Station and Setup Website  Why did I work for SRRC???  Higher salary $$$$$  A stabile job  To be a civil servant  Why did I quit this job???  Radiation  A bit too stable ???? $$$$$ lost ~1/3

6 Self Introduction - III  ITRI 量測中心 (1997/7 ~1999/6)  Division: 超音波部  Digital system designer for Ultrasonic Diagnostic System  Developed the controller of whole system and system platform  Built up the FPGA design flow (Actel) and Interfaced the ASIC house.  Developed the Nebulizer （霧化器 ) product  Why did I work for ITRI???  Trend in biological medicinal engineering  A good opportunity because the whole division would be spun off from ITRI.  A good training environment, Graduate student alike  Why did I quit this job???  Manager did not want to spin off  Get back to IC design field

7 Self Introduction - IV  AMIC (1999/6 ~2000/2)  Division: Consumer Product  Developed the 8 bit uP based audio decompression chip  Why did I work for AMIC???  IC design trend for acoustic recognition  Recall the IC design capability  Economic Issues  Why did I quit this job???  主管操守有問題 ……..

8 Self Introduction - V  Core Technology Division  Responsible for MIPS-clone CPU implementation and migration in different process.  Companion IP designer  SIS – ARM Service Center  Transferring ARM’s framework of SoC technology to Faraday  Built up the ARM developing flow in Faraday  Customer service and promotion for ARM core based ASIC About Faraday

9 Self Introduction - V  IP Service Development  Post-Sales for 8bit uP (80xx), 32bit processor core such as ARM core, MIPS-clone core and Companion IP  Pre-Sales for SoC based IP and Related Platform  OBD (Overseas Business Department)  Responsible for Overseas ASIC/IP project  Responsible for the development of SoCreative! Platform

10 Self Introduction - V  IBO 國際營運中心 – Field Marketing Development  Research in Strategy Marketing  Come out the new product plan and then  Research in specific topic for subsidiary company  Technical supporting for Faraday’s customer in Europe, Japan and USA  SoC based ASIC project cooking  Product Promotion  Resource backup

11 Contents  Self Introduction  Sharing in Working Experience  Job Opportunities  Open Discussion

12 My Personal Opinions – I  Job Position 現在 未來 ＝ 工作資歷的累積 - 影響未來 滾石不生苔 – 頻換工作 專業設計能力 RD Project Leader CTO Project Manager ? Years 立志：我要做 RD.. 我真的是 RD.. 我還是 RD

13 My Personal Opinions – II  Job Position 現在 未來 ＝ 立志：我要做 RD 我還是 RD???? RD Digital Design FAE (Post-Sales) Promotion (Pre-Sales) Marketing $$$$

14 My Personal Opinions – III  Job Outlook - Your Target - VS. $$$$$ 工作 能力好 ＋公司營運好 ＝＄＄＄＄＄＄＄（機會＋運氣） 能力不好 ＋公司營運好 ＝＄＄＄＄＄＄ （運氣） 能力好 ＋公司營運不好＝＄＄ （找機會） 能力不好 ＋公司營運不好＝＄ (????, 向上努力吧 !) 不要幻想在科學園區就能賺大錢 不是每一個人都在 聯發科技 工作靠實力, 賺錢靠運氣

15 My Personal Opinions – IV  你即使離職了，公司 ……… 還是活得好好的 ……… ^_^  拋開本位主義 1. 為何 Sales 老是接一些奇怪的案子 ? 2. Sales 只出一張嘴？ 3. 產品 Delay 一下有啥關係 ? 1. 公司業績不好, 老板催訂單 2. 接案子 - 沒問題 Design 有 Bug - 沒關係 Bug 無解,Re-design- 沒辦法 3.Schedule Delay 錢收了, Time-to-Market (?) RD/Project Leader Marketing/Sales

16 My Personal Opinions – V  坐這山  望那山  他都沒做什麼事 ?  Sales – 尊嚴, 客戶財務結構, 業績 ……  Designer – 研發, Schedule 壓力  Ｍ arketing – 市場分析, 產品決策  Service 人員沒啥技術能力 ?  罰站, 被罵, 向客戶賠不是 ……  總機小姐甜美的聲音 ………. 客戶也會時常問候 ……… ^.^ 公司會賺錢 : 研發, 銷售, 客服 大家努力而成，絕非個人

17 Suggestions  肯定自我 / 他人工作價值 – 工作愉快，相處融洽  積極主動 – 多做未必是錯，機會在將來  廣結善緣 – 圈子很小，到處是熟人  溝通能力 – 各式各樣職務  語文能力 – Global Company (D-Link, BenQ, Acer, Foxconn, TSMC, UMC,..) => CEO is Italian.  國際觀  Customer from Great China, Europe, Korea, Japan, USA  Competitor in WW  Business in WW  No Time Lag for Internal Business EUP USA 17:00 01:00 09:00

18 Contents  Self Introduction  Sharing Working Experience  Job Opportunities  Open Discussion

19 Job Opportunities  Head Count : 2 for Field Marketing  Strategize, Conceive, Research RISC CPU and SOC Related Product Plan  Technical promotion, support on platform-based SoC design  Needed Background  Major in EE or Computer Engineering  Experience in IC/SOC Integration, IP Technology or Chip-Set Design (at least 4 years) Frank Cheng Frank Cheng 鄭順發, ext

20 Q & A Thank You!

21 Faraday: at a Glance  Spun off from UMC in 1993  UMC owns 20%+ of Faraday  UMC & Faraday still share same chairman  Strategic IP partnership  Fabless ASIC and IP provider  Solid business model of 45% GM, 25% net, 30%+ CAGR  Diversified customers & markets  Listed in Taiwan exchange in 1999  Today ’ s operation  500+ employees worldwide, 330+ in R&D

22 Contact Faraday Faraday USA Sunnyvale, CA TEL: Faraday Netherlands Amsterdam TEL: Faraday China Shanghai TEL: Faraday Japan Tokyo TEL: Faraday Taiwan (HQ) Hsinchu & Taipei TEL:

23 Million NTD CAGR = 37.68% Financial Achievements Million USD 2004 revenue: $155M 35%+ CAGR since ‘97

24 Faraday Offers ASIC Front-End Architecture Specifications Behavior Modeling RTL Code Generation Synthesis Gate Level Verification Test Pattern Generation Post Layout Verification ASIC Back-End Mask Tooling Wafer Manufacturing Services IC Packaging Services Circuit Probing & Final Testing Product Engineering IP System-on-a-Chip Libraries / Memories Microprocessors Digital / Analog Platform Reliability Test Services Physical Implementation ASIC Design Services, SoC Design Services, Proven IP Solutions

25 ASIC Infrastructure & Expertise  More than 100 people in ASIC Technology  ASIC implementation, testing, yield, and FA (70)  Design methodology & integration (35)  Production planning, logistic, and quality (25)  10 years of experience on average  More than $50M invested in infrastructure  eRD, ERP, Testers, ESD machine, die/wafer bank  Complete integration of R&D, FIN, customer project, and production shipment  More than 200 project tape-outs in ’ 04 alone  40% test chips  10% in 0.13um, including four customer ASICs

26 PS: Ex-IP sales revenue 2003 Sales Breakdown (2-1) By application

Sales Breakdown (2-2) By customer typeBy geography

ASIC IP AND BEYOND Technology Roadmaps

29 Cell Library Roadmap nm 130nm 90nm SP-Rvt / Low-K 0.15µm SP 0.15µm 65nm 65nm SP 90nm LL-Hvt / Low-K 130nm L130E SP / FSG 90nm LL-Rvt / Low-K Legend Description ： Rvt ： Regular Threshold Voltage Hvt ： High Threshold Voltage SP ： Standard Performance LL ： Low Leakage ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com

30 Memory Compiler Roadmap µm 130nm L130E Fusion / FSG 130m L130E HS / FSG 90nm 65nm 0.15µm SP 130nm 90nm SP-Svt / Low-K 65nm SP 130nm L130E SP / FSG 130nm L130E LL / FSG 90nm SP-Hvt / Low-K 90nm SP-Svt / FSG 90nm LL-Rvt / Low-K ＊ ＊ Legend Description ： Rvt ： Regular Threshold Voltage HS ： High Speed Hvt ： High Threshold Voltage SP ： Standard Performance LL ： Low Leakage ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com ＊ ＊

31 Analog Essential IP Roadmap 130nm 0.18µm 0.25µm 0.35µm 90nm 0.15µm PLL 130nm HS / FSG 400MHz PLL 90nmSP / FSG 1GHz PLL RC-OSC 130nm RC-OSC nm SP / FSG 2GHz PLL 130nm HS / FSG 1GHz PLL DLL 130nm HS / FSG 1.6GHz PLL 130nm HS / FSG 533Mb/s DLL 130nm HS / FSG 400Mb/s DLL 90nm SP / FSG 800Mb/s DLL 130nm HS / FSG MiniPLL 90nm SP / FSG RC-OSC 0.15µm 1.5V 400Mb/s DLL 130nm HS / FSG Wide Range DLL 0.18µm GII MiniPLL 0.15µm 1.5V 300MHz PLL VDT 90nm VDT 130nm HS VDT 0.18µm GII VDT PWM 0.18µm GII > 50mA PWM 130nm HS > 50mA PWM 90nm SP PWM POR / BG 0.18µm GII POR 130nm BG 0.15µm POR 90nm BG REG 0.18µm REG 0.15µm REG 130nm REG 90nm REG 0.18µm GII RC-OSC Legend Description ： HS ： High Speed SP ： Standard Performance ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com

Sigma-Delta Codec RSDS TX 3-channel DAC 130nm 0.18µm 0.25µm 0.35µm 90nm 0.15µm Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: ADC DAC LVDS TX / RX 130nm 16-bit Audio Codec µm 10-bit 80MHz ADC 130nm 8-bit 125MHz ADC 0.25µm 10-bit 150MSPS 3-channel DAC 0.18µm 8-bit 44MSPS DAC 130nm 12-bit 100MSPS DAC 0.25µm 16-bit Audio Codec 0.18µm 10-bit 150MSPS 3-channel DAC 130nm 10-bit 150MSPS 3-chanel DAC 0.25µm 18-bit Audio Codec 0.18µm 16-bit Audio Codec 0.25µm 6-bit 44MHz 130nm 10-bit 80MHz ADC Analog Data Conversion & Serial Link IP Roadmaps 0.35µm RSDS 0.35µm LVDS 0.25µm RSDS 0.25µm LVDS 0.18µm LVDS 0.25µm mini LVDS 0.18µm 1.8V LVDS 130nm LVDS

33 USB IP Roadmap 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm FPGA USB2.0 2-port Host PIE FUSBH210 USB 2.0 OTG PHY USB 2.0 OTG PIE USB 2.0 Host PIE 90nm USB 2.0 OTG PHY USB2.0 2-port PHY 130nm USB port PHY FPGA USB2.0 Host PIE FUSBH200 FPGA USB2.0 OTG PIE FOTG µm USB2.0 OTG PHY 130nm USB2.0 OTG PHY HS 130nm USB2.0 OTG PHY SP 0.18µm USB 2.0 Device PHY v36 USB 2.0 Device PHY Legend Description ： HS ： High Speed SP ： Standard Performance ＊ ＊ ＊ Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com

34 Serial-ATA IP Roadmap Serial-ATA Controller Serial-ATA PHY 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: FPGA Serial-ATA Controller With AHB I/F 130nm 3Gbps SATA PHY 130nm Multi-Port SATA PHY

35 PCI Express IP Roadmap Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm PCI Express Controller PCI Express PHY FPGA PCI-Express Controller End-point (PIPE) 130nm Multi-lane PHY x 4 lane 130nm Single-lane PHY x 1 lane 0.18µm Single lane PHY x 1 lane

36 Ethernet Roadmap 130nm 0.18µm 0.25µm 0.35µm 90nm 0.15µm 10/100 Ethernet PHY 130nm HS 10/100 Ethernet PHY 0.18µm 10/ port Ethernet PHY 0.25µm 10/100 Ethernet PHY Legend Description ： HS ： High Speed ＊ ＊ Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com

37 Digital IP Roadmap Communication Peripheral MS Pro Card Controller LCD Controller 10 / 100 MAC Gigabit MAC TV Encoder MPEG4 Encoder / Decoder DES / 3DES Security Engine Wireless LAN a / b / g MAC / BBP DDRI Controller Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: DDRII Controller Multimedia

38 Faraday CPU Roadmap Clock (MHz) µm FA µm FA nm HS FA526 HS 130nm FA nm LL FA526L 130nm HS FA626 90nm HS FA626 Note: Left and right edges indicate Tape out and Silicon proven schedule respectively. For more details please visit our website at: www. faraday-tech. com 130nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm Legend Description ： HS ： High Speed LL ： Low Leakage ＊ ＊ ＊ ＊ ＊

39 Faraday StarCell ™ IP  DMA Controller  Static Memory Controller  SDRAM Controller  UART  Timer  Watchdog Timer  Real Time Clock  Interrupt Controller  SD Host Controller  KBD / Mouse Controller  Synchronous Serial Port  Fast IrDA Controller  CF Host Controller  Memory Stick Host Controller  GPIO  10 / 100M Ethernet MAC / PHY  PCI 33 / 66  USB 1.1 Device Controller / PHY  USB 2.0 Device Controller / PHY  Smart Media Host Controller  USB 1.1 FS / LS OTG  DDR Memory Controller  LCD Controller  TV Encoder Faraday provides a comprehensive portfolio of Peripheral IPs, as the following list,which are available right now ：

40 DSP Roadmap Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: nm 0.18µm 0.25µm 0.35µm 90nm FPGA 0.15µm

41 Networking Platform Roadmap Q4 Q1 Q2 Q4 NetComposer-I: 500MHz 32-bit CPU (FA626, 130nm, 1.08V, 125°C) GMAC (*2) Switch Fabric Coherence Engine MPCA (Customer Engine) PCI-X 133MHz DDR-333 Controller Net- Composer-I (NC-I) Q3 NetComposer-II: 600MHz 32-bit CPU (FA626, 130nm, 1.08V, 125°C) 8 Programmable Serdes GMAC (*2) Switch Fabric Coherence Engine MPCA (Customer Engine) PCI-X 133MHz DDR-400 Controller with ECC Net- Composer-II (NC-II) Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at:

42 Multimedia Platform Roadmap Q3 Q4 Q1 Q3 FIE8100: FA526 Cache 16K/16K MPEG4 Codec 36fps JPEG standard Codec USB 2.0 Device TFT LCD controller TV encoder FIE8100 Q Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: FIE8150 FIE8150: FA526 Cache 16K/16K MPEG4 Codec 30fps JPEG standard Codec TFT LCD, PCI, USB 2.0 OTG, IDE 10/100 Ethernet WLAN802.11a/b/g 300K MPCA (Metal Programmable Cell Array) Q4 FIE8200 FIE8200: FA526 Cache 16K/16K MPEG4 Codec 30fps JPEG standard Codec ISP, 2D/3D Graphic Engine 300K MPCA (Metal Programmable Cell Array)

43 IA Platform Roadmap 0.13µm process FA501, USB OTG 20-bit Audio DAC, LCD controller, TV encoder, IDE/CFII 2006 Q1 Q2 Q4 Q Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: Q1 WLAN + VoIP USB OTG FIE µm process FA526, USB OTG Audio Codec, LCD controller, IDE/CFII FIE µm process FA526, FD WLAN g, LCD controller FIE7010 PAP FIE µm process FA501, USB OTG WLAN g, Audio/Video Codec, LCD controller, TV encoder Ultra Low Power PAP Wi-Fi Phone Ultra Low Power Wi-Fi Phone UWB FIE µm process UWB MAC+BBP+RF Wireless USB

44 Structured ASIC Family Roadmap Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: µm 0.15µm 0.25/0.22µm 130nm nm 0.18µm LL MPCA MPIO 0.18µm GII MPCA 0.15µm SP MPCA 130nm HS MPIO 90nm SP-Hvt MPCA Library 90nm SP-Hvt MPIO 0.15µm SP MPIO 130nm TEMPLATE FIT nm LL MPIO 130nm SP MPIO 0.18µm GII MPIO 130nm TEMPLATE FIT nm TEMPLATE FIT nm TEMPLATE FIT nm TEMPLATE MP-Ware 130nm TEMPLATE Producer II 90nm LL-Hvt MPCA Library 90nm LL-Hvt MPIO 130nm HS MPCA 130nm LL MPCA 130nm SP MPCA ＊ ＊ ＊ ＊ ＊ ＊ Legend Description: Hvt ： High Threshold Voltage SP ： Standard Performance LL ： Low Leakage MPCA ： Metal Programmable Cell Array MPIO ： Metal Programmable IO HS ： High Speed ＊ 0.18µm 130nm 0.35µm 90nm FPGA 0.15µm ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊ ＊

45 Welcome to join Faraday