Application of through-silicon-via (TSV) technology to making of high-resolution CMOS image sensors Name: Qian YU Student ID: 20221416

Outline Why TSV? TSV process? Application in image sensors?

Size Effects due to Electron Scattering Why a TSV? Size Effects due to Electron Scattering 1) Scaling conventional wires More scattering at wire surfaces Resistivity increases as cross-sectional dimensions scale down Surface and gain boundaries Gain boundaries 2) TSV Better electrical performance Lower power consumption Wider data width Higher density Smaller form factor Lighter weight surface Interconnect length dose not scale down with transistors 3D is can effective way to scale John H. Lau, “Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration” Electronic Packaging, Vol.136, 040801 (2014) W. Steinhögl, et al., “Size dependent resistivity of metallic wires in the mesoscopic range,” Physical Rev. B vol. 66, 075414 (2002)

3D integration key technology Why TSV? 3D integration key technology Small Form factor Faster interconnects & reduced power consumption Heterogenous Integration & high density integration An increasing number of companies, such as IBM, Xilinx, Samsung and Bosch, are taking 3D through-silicon-via (TSV) technology to the commercialization phase From IMEC 2011 Ko, C. T., and Chen, K. N., “Wafer-Level Bonding/Stacking Technology for 3D Integration,” Microelectron. Reliab., 50(4), pp. 481–488 (2010).

From Yole Development Company, 2012 TSV trend The global 3D TSV semiconductors packaging, assembly and test market will reach the $8B business value by 2017 ITRI (Taiwan) tapes our 3D-IC stack with TSVs using Cadence design system in 2012 From Yole Development Company, 2012 http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=101512_ITRI

Via first/FEOL (front-end-of-line): TSV process Categories: Via first/FEOL (front-end-of-line): Fabricate vias in blank wafer Fabricate CMOS circuitry Grind to thickness，Used in high brightness LED package Si-substrate IC Clean Wafer TSV making and filling Wafer process Wafer thinning Bumping Poly-Si Fabricate CMOS circuitry Fabricate vias in blank wafer Grind to thickness，Thermal budget limitation Via last/BEOL (Back-end-of-line): Si-substrate IC TSV making Wafer process Wafer thinning Metal plating Bumping Souriau, J. C., Sillon, N., Brun, J., Boutry, H., Hilt, T., Henry, D., and Poupon, G., 2011, “System-on-Wafer: 2D and 3D Technologies for Heterogeneous Systems,” IEEE Trans. Compon. Packag. Manuf. Technol., 1(6), pp. 813–824.

Etching: make high aspect ratio via. Sputtering: insulation material between TSV and substrate; seed layer. CVD: conductive material (Poly-Si, Cu, W) deposition into the via. CMP: Remove extra material deposited by CVD; wafer thinning. TSV process flow PR Si-substrate Handle wafer Inter-player Adhesive Passivation layer Etching Sputter SiO2 Ta/TaN/Au CVD Conductive paste CMP Bonding pad Backside lithography Deep Si etching SiO2 etching Side wall insulation Conductive material filling (Cu)

TSV application in image sensors for smart imaging systems 2 imager roadmaps with different methods: Traditional: scaling to smaller pixels: - Equal chip size - Higher resolution -lower sensitivity Integration/ packaging method: 3D integration with backside illuminated image sensor Enables advanced imaging systems

Advantage of TSV technology in image sensor Main advantage is to reduce the size of the image sensors Advantages: Smaller footprint Reduced capacitance leads to faster & lower power interconnect Buttability with minimal area loss Applications: Consumer imagers Large area tiled imagers endoscopes Makoto Motoyoshi, “Through-silicon-via,” Proceedings of the IEEE , Vol. 97, No. 1, January 2009.

System architecture of an imaging system on a chip-stack Stacking of multiple layers: Detection layer + Read out IC layers - Example: passive photodetector layer + analog Readout IC + digital image processor Advantages: General: optimization of CMOS technology for different layers Imager system: Vertical parallel readout chain allows higher speed Larger area per pixel allows complex electronics per pixel Low capacitance interconnect to digital image processor allows high speed and low power From IMEC 2011

One stacking package of back-illuminated (BI) CMOS image sensor by SONY company The top layer of Sony’s stacked images sensor is a BSI sense layer stacked on the readout/image processing. Large TSVs are used to create vertical interconnects to the peripheral electronics. (Image courtesy of imec and Sony) Shunichi Sukegawa, “A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor” IEEE International solid-state Ciruits Conference, 978-1, 2013