1. ３D Integration for SOI Pixel Detector
T-Micro
３D Integration for SOI Pixel Detector
Makoto Motoyoshi
(T-Micro)
Thank you Mr. Chairman. Good evening Ladies and gentleman. I will be talking about versatile 3D bonding technique using u-bump for Pixel detector.

2. Contents 1. Motivation 2. Technologies and issues
Device target
2. Technologies and issues
SOI Pixel detector
process flow
Yield
process issues and counter measurements
3. Cost down technique of 3D stacking
4. Summary
These are contents of my talk. In this presentation, first I’m gonna talk about the motivation of the present work, mentioning about the target device and target device spec. followed by Then, I will show you Technical issues After that I will Finally, I will make brief summary and talk about future plans. In paticular

3. Target of our 3D technology
1. Motivation
Target of our 3D technology
Realize High Speed Parallel Processing Pixel Sensor with Memory
32 x 32 pixels
6M/4096(5859)pixel arrays
Pixel array (BSI type)
(0,3)
(0,2)
(0,1)
(0,0)
1024 pixel data (serial)
5859 parallel data
Dec
ADC
Decoder
AD Converter
1024x12 bit data (serial)
5859 parallel data
32 x 32 x 12 (12288k) n
Memory Array
DSP

4. 1. Motivation
Target 3D Technology
108
107
106
105
104
103
Number of TSV (cm-2)
10% 5% 1%
TSV
area ratio
TSV diameter
=TSV pitch x 1/2
TSV pitch (um)
RC Delay 2 4 6 8 10 12 5 15 20
RC Delay (fs)
101
100
10-1
10-2
10-3
TSV length, diameter (mm)
length
diameter
M. Koyanagi et al.,
IEEE Trans. Electron Devices,
VOL.53, NO.11, pp , 2006
- Via last process
- Interconnect density 104~105/cm2
- Area penalty ≤1 %
- Good manufacturability (high yield, reliability)
- Low process temperature
- Low cost
TSV and μ-bump technology with the pitch less than 5μm

5. Stacked SOI Pixel detector
Back gate
electrode
Bond Pad
Charged Particle
BOX(upper tier)
Metal interconnect
Bump junction
BOX(lower tier) p+ n+
+ -
buried p-well
This slide shows the birds-eye view of silicon base stacked SOI pixel detector . Pixel detector at collider is designed to collect the information on particles which come from the point where mother particles collide. Differ from the image sensors for digital camera, this device need to detect fewer and much higher energy particles which pass through the chip. Incident charged particle generate a bunch of hole-electron pair along the trajectory in high resistance silicon substrate. And holes are collected by buried pwell layer and sensed by read-out circuit. As the performance improvement, 3D integration is expected to increase space and time resolution and functionality such as counter, memory etc. in a pixel
n--
Si sensor
(high resistivity Substrate)

6. Process flow (1) < Lower Tier > < Upper Tier >
(a) Start with FD-SOI
device wafer M4 M3 M2
MOST M1
Active Si~50 nm
BOX:200 nm
BOX
BOX
High R-Si Si
MOS Tr Si
*FD: Fully Depleteｄ Si
µ-bump
µ-bump
(b) µ-bump forming
High R-Si Si Si Si Si Si
Upper tier
Next two slides show the key fabrication process steps. Both Lower tier and upper tier are fabricated in a 0.2um FD-SOI CMOS process with 4metal interconnect layers. Top metal is used for Vdd, GND lines and bump pads Thickness of buried oxide and SOI are 200nm and 50nm respectively. After planarizing surface, In –u-bumps are formed using evaporation technique. After face to face infrared alignment, upper chip is temporary bonded followed by adhesive injection and permanent bonding.
adhesive
(c) Chip bonding
-face to face infrared alignment
-temporary bonding
-Adhesive injection
-permanent bonding (<200℃)
Lower tier
High R-Si

7. SOI pixel detector Chip
(After forming u-bump)
In μ-bump
10µm
Detector Array
Upper tier

8. Selection of Wafer/Chip bonding technology
Adhesive Si
SiO2
Metal
μ-bump
Polymer adhesive bonding
SiO2 fusion bonding
Metal fusion bonding

9. Selection of Wafer/Chip bonding technology (2)
1. Motivation
Selection of Wafer/Chip bonding technology (2) Si Si
Cu/Sn bump
Metal bump Si Si
Metal eutectic bonding
Bumping (Pb/Sn, Au, In)

10. Yield model Yield Model of LSI Y= Y0・Y1(D0, A, α)
Y0 :　Systematic yield
Y1 :　The fraction of chip sites without 　　　
　　　　process related effects and circuit 　
　　　　sensibility
A : Chip Area
D0 : Density of defects
α : Distribution parameter of defects
Defect source
　　- dusts or other particles in the environment, solution,
process chamber in the production equipment
- pattern defects due to ununiformity of material
- oxide defects caused by process damage
- statistical factor
etc.

11. Yield model Y1 = exp (-D0A) 1-exp(-D0A) Y2= D0A 1-exp(-2D0A) Y3= 2D0A
Yn :　The fraction of chip sites without 　　　
　　　　process related effects and circuit 　
　　　　sensibility
A : Chip area
D0 : Density of defects
F(D)
Y1　=　exp (-D0A) D0
2D0
F(D) D0
2D0
1-exp(-D0A)
D0A 2
Y2=
F(D) D0
2D0
1-exp(-2D0A)
2D0A
Y3= 1
(1+SD0A)1/s
S0
Y4=
S=1.0
F(D)
S=0.1
S: shape parameter D0
2D0

12. Yield Prediction Y=exp(-D1A) Yield 1 Y= （1+D0A） Initial manufacturing
Chip Area

13. Yield and reliability 1. Motivation dusts or particles No failure
S/D
S/D
S/D
S/D
S/D
S/D
No failure
or reliability problem
No failure
failure
Oxide CVD
CMP
Via patterning
Form metal interconnect
S/D
S/D
S/D
S/D
S/D
S/D

14. 1. Motivation
Yield and reliability
dusts or particles
S/D
S/D
S/D
S/D
S/D
S/D
No failure
or reliability problem
No failure
failure
Oxide CVD
CMP
Via patterning
Form metal interconnect
S/D
S/D
S/D
S/D
S/D
S/D
We can only detect this failure from electrical testing.

15. 1. Motivation
Yield and reliability
dusts or particles
S/D
S/D
S/D
S/D
S/D
S/D
No failure
or reliability problem
No failure
failure
Oxide CVD
CMP
Via patterning
Form metal interconnect
S/D
S/D
S/D
S/D
S/D
S/D
In case of bonding wafer/chip on wafer /chip surface with dust,
Upper Chip
Lower Chip
If the bonding method which needs microscopic smoothness and cleanliness, bonding yield will be affected by defect density of dusts and particles.
So we have chosen the bump bonding with adhesive injection.

16. Wafer Bonding Method (Tohoku University/T-micro)
1. Motivation
Wafer Bonding Method (Tohoku University/T-micro)
Bump size (~μm) >>dust or particle size (≤0.2μm) Si
dust
Adhesive Si Si Si Si Si
Wafer or Chip Alignment
Temporary Bonding
Adhesive Injection
In μ-bumps do not have enough mechanical strength,
so the combination use of adhesive is indispensable.

17. SOI pixel detector Chip
After Si removal
Detector Array /Peripheral Circuits
so the circuit layout of upper chip is superimposed on the circuit layout on lower chip and easily detect voids between two tiers.
Voids

18. Process flow (2) (d) Bulk-Si removal (e) Pad patterning
High R-Si
Bond Pad
Passivation
Back gate adjust electrode
(e) Pad patterning
and passivation
And finally bond pads and back gate adjust electrodes for SOI transistors are formed on BOX surface followed by forming passivation
High R-Si

19. Void problem
Void
Void
Void
Void
In u-bump bonding has good electrical characteristics and reliability. 2.5um sq. bump resistance is around 30mohm, but mechanical strength is not enough for bonding of chips with warpage. Therefor bonding combined with adhesive injection is indispensable. At early development, we have cheched simple test device and confirm no voide using IR microscope. But using SOI circuit test chip for development popcorn crack, IR microscopy

20. Mechanism of void formation (1)
Uniform pressure change
Bump connection
adhesive
Upper tier
Lower tier
(a) Simple test device
voids
(b) Circuit test device
No void in pixel array
Peripheral circuit
Detector array
non-uniform pressure change
Uniform pressure change
Top metal
void
Top metal
Passivation layer
Top metal
adhesive
interlayer
Si-sub
Bump connection

21. Mechanism of void formation (2)
Scribe line
Injection
line
Chip area
Adhesive flow speed
Pumping action > capillary action　　 F1 F2 F3 F4 F5
F1, F3, F5 > F2, F4
Void
Pumping action < capillary action　　
F1, F3, F5 < F2, F4 F1 F2 F3 F4 F5
Void
Chip area
Injection
line

22. Mechanism of void formation (3)
Adhesive flow rate
Chip area F1
High density
bump area F2
Void F3 F4
F1, F4 > F2, F3

23. Pixel detector chip after Si removal
Optimize
- bump layout
- differential pressure of
adhesive injection
- process temperature
(control the viscosity
of adhesive)
- wettability of adhesive
Void
Void
Void
(a) before improvement
(b) after improvement

24. Two types of pixel detector chip
A pattern (5mm x 5mm)
B pattern (5mmx 5mm )
upper left corner
upper right corner
after Si removal
left lower corner
right lower corner
Finished Chip

25. Cross sectional SEM image of pixel array
Back gate Metal
MOS Tr
BOX(UT)
M1(UT) UT
M2(UT)
M3(UT)
In bump
M4(UT)
Adhesive
M4 (LT)
M3(LT)
M2(LT)
M1(LT) LT
BOX(LT)
5μｍ
UT: upper tier
LT: lower tier

26. Poor wettability

27. 2.0μm In Ti
Al5%Cu

28. In bump vs In/Cu bump Bump Resistance (Ω) In In/Cu 10000 1.0 0. 1 0.01
2 x 2 um x 2440 bump daisy chain
10000
1.0
Bump Resistance (Ω)
0. 1
0.01 In
In/Cu

29. Stacked SOI Pixel Detector
Summary-Technology selection chart
Stacked SOI Pixel Detector
SiO2 fusion
bonding
metal fusion
metal eutectic
Bumping
Polymer adhesive
Cu/Sn
Pb/Sn Au In Cu
Manufacturability
Bumping
Wafer/chip
bonding
Low process
temp.150~200℃ In
Combining
Adhesive injection
Overcome weak mechanical strength
Process issues
Void
Chip shift

30. Prototype of 8” Self-Assembled Chip Bonder
This slide shows Photomicrograph of a New Self-Assembled Chip Bonder we have developed.
This equipment mainly consists of high-precision stage, IR camera, gap sensor, and weight sensor and piezo actuator.
The stage temperature can increase upto 400 degreeC.
And maximum bonding pressure is one thousand kg.

31. Alignment accuracy: ~ 400 nm
Simultaneously picked-up 500 chips (5mm×5mm)
Liquid array on
an 8-inch wafer
A large number of
self-assembled chips
Hydrophilic bonding area
KGDs
Chip release
Self-assembly
Liquid on hydrophilic
area formed on the wafer
Self-assembled KGDs
Liquid
KGD
180mm
50mm
150mm
Self-Assembly Process with 8-inch Wafer
Multi-chip pick-up plate
Alignment accuracy: ~ 400 nm
このスライドはアニメーションを使用して説明します。
I’ll show you a self-assembly process with 8inch wafer.
In this case, First, a multi-chip pick-up plate transfers more than 500 chips from chip tray to an 8-inch wafer.
Here, we use 5-mm-square chips.
Then, liquid are provided on the hydrophilic bonding area formed on the 8-inch wafer, like this.
After pre-alignment and chip release, the many chips are precisely aligned to the wafer, like this.
The alignment accuracy was found to be approximately 400 nm.
By optimizing the self-assembly conditions, we can further increase the alignment accuracy.

32. 200 mm
図４　試作製造装置で多数のチップを仮接着したウェーハの全体写真
Confidential / Koyanagi Lab

33. Conclusion 3D LSI Integration technology using minimum 5μm pitch bump
　　is verified using SOI stacked pixel detector as circuit level test 　
　　device.
In this technology, adhesive injection is found the key technology. Optimizing layout, process parameter and adhesive injection method, this process have completed without void.
The dispersion of bump resistance is still high, the following optimization are still ongoing.
　　 Improvement of wettability between bump and pad
Introducing the new Cu/In IMC bonding
In further development of wafer /chip bonding with few μm pitch bump , it might be necessary to optimize the gap between tiers and volume of bump metal.