Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors Javier de San Pedro, Nikita Nikitin, Jordi Cortadella and Jordi.

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Presentation transcript:

Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors Javier de San Pedro, Nikita Nikitin, Jordi Cortadella and Jordi Petit Universitat Politècnica de Catalunya (Barcelona) Project funded by Intel Corp.

Outline Introduction – Architectural exploration of CMPs Physical planning – Integration with architectural exploration – Floorplanning and wire planning technology Results and conclusions NOCS 20132

Designing a Chip Multiprocessor NOCS CMPCMP Off-Chip Memory DSPDSP GraphicsGraphics Data Mining BioinformaticsBioinformatics How many cores? How much L2/L3 on-chip cache? Interconnect: mesh/ring/bus? How many memory controllers?

Automated exploration Models (performance/power) Cores On-chip caches Off-chip memories Interconnect fabrics Cache protocol Workloads Architectural configuration Number of cores Cluster size L2/L3 size Hierarchical interconnect Memory controllers Exploration tool Constraints Area Throughput Power NOCS Huge design space: Billions of configurations

Our exploration flow NOCS 2013 Simulation Analytical Modeling* 5 Architectural configurations Promising configurations *N. Nikitin et al. "Analytical Performance Modeling of Hierarchical Interconnect Fabrics.“ NOCS 2012

Configuration example NOCS C2C2 L2L2 C2C2 L2L2 C2C2 L2L2 L3L3 Bus C2C2 L2L2 C2C2 L2L2 NINI RR C1C1 L2L2 - 6x4 mesh, 24 clusters - total 144 cores - 6 cores/cluster - 1 C1, 128K L1, 256K L2 - 5 C2, 64K L1, 96K L Mb total shared L3 Throughput = IPC - 6x4 mesh, 24 clusters - total 144 cores - 6 cores/cluster - 1 C1, 128K L1, 256K L2 - 5 C2, 64K L1, 96K L Mb total shared L3 Throughput = IPC

Min area, but … Unbalanced aspect ratio L2 not adjacent to cores Uneven distribution of ring routers Motivation for physical planning NOCS CC L2L2 CC L2L2 CC L2L2 CC L2L2 rrrr rrrr rr rr RR L3L3 NSWE Block area is used during exploration

Abutability in tiled CMPs NOCS 2013 N S E W 8

Over-the-cell routing ISPD 2013Tiled CMPs Cache Core 9  wires Router 1000 wires  10 µm

Physical planning NOCS 2013 Simulation Analytical Modeling L3L3 RR Local IC L2L2 CC CCL2L2 L3 10 Physical Planning Estimations: Area Wirelength Routability

Floorplanner Slicing structures & Simulated Annealing* Lightweight maze router Constraints: – Adjacency (Core  L2) – Balanced links (rings) – Maximum length for critical nets NOCS D.F. Wong and C.L. Liu, “A New Algorithm for Floorplan Design” DAC 1986, pages V HH V

Wire planner SAT-based approach for gridded routing Grid unit: link width (  wires) Customizable for any type of Boolean-encoded constraints (abutability, 1D/2D routing, …) NOCS 2013 Top view Cross-section view 12

Filtering floorplans NOCS Area limit

After physical planning NOCS

Conclusions Physical planning has significant impact during architectural exploration of tiled CMPs Future work: – New topologies (mesh of rings) – Multi-module memory floorplanning – Regularity and choppability NOCS