1. Interconnect Complexity-Aware FPGA Placement Using Rent’s Rule G. Parthasarathy Malgorzata Marek-Sadowska Arindam Mukherjee Amit Singh University of California, Santa Barbara

2. 2 9/7/00 Outline u Motivation u Rent’s Parameter u Analysis u New Placement Algorithm u Results u Conclusions u Future Work

3. 3 9/7/00 Motivation u 80-90% of die area = interconnects s increased programmability u routing resource utilization (RRU) is low s 100% logic utilization u unused LUTs -> better RRU u maybe at the cost of increased area? s Maybe not! u interconnect complexity guided placement - Rent’s parameter

4. 4 9/7/00 Rent’s Parameter u Common measure for Interconnect Complexity N io = K N g P N io – Number of IO pins/terminals external to the logic partition K - Average number of interconnections per LUT N g – Number of LUTs in a logic partition p – Rent’s parameter after E.F.Rent E.F.Rent,1960 Landman, Russo, 1971

5. 5 9/7/00 Local Rent’s parameter P l d u Complexity Varies across design. u Solution – Use local interconnect complexity measure based in interconnect length distributions. (Van Marck et al.,95) u Reduces to Landman’s Rent’s exponent for uniform design at the top level

6. 6 9/7/00 Rent’s Parameter Van Marck, Stroobandt, Campenhout, 1995  p :  (log N i ) /  (log L i ) p – Rent’s parameter L i - length of a net N i - number of nets of length L i

7. 7 9/7/00 Rent’s Parameter log N i log L i pldpld pldpld VPR pldpld MVPR

8. 8 9/7/00 Analysis u Consists of LUTs, connection boxes and switch-boxes u Regular 2-D mesh array of unit tiles FPGA Architecture

9. 9 9/7/00 FPGA Fabric Min-Size-Up u Definitions s Pa – Rent’s parameter for Architecture s Pd – Rent’s parameter for Design u Case 1: Pd <= Pa s Design routable. Try to get best placement. u Case 2: Pd > Pa s Design Un-routable. Need more resources. s Solution – Increase FPGA fabric size by scaling factor C Pd PaPd g Pa g Pd g NC ) K(C.NK N N io   

10. 10 9/7/00 New Placement Algorithm u Simulated Annealing - VPR u scale-up fabric by C u modify VPR’s existing Cost Function u | p l d - p l a | used as scaling factor for bounding-box based cost function u uniform distribution of interconnect complexity    n net q(i) Function Crossing Track Bi)ox_length(Bounding_b plapla pldpld 1i (1+ )

11. 11 9/7/00 Place-and-Route CAD Flow u Generate Benchmarks s Known Pd s Uniform Distribution u Map to Net-list u Place-and-route s VPR s MVPR u Compare pldpld plapla > ? scale-up fabric by C yes no use MVPR placed and routed design

12. 12 9/7/00 Results - Benchmarks gnl generated ckts random ckts - ISCAS benchmarks p1dp1d p2dp2d p3dp3d p4dp4d p5dp5d p6dp6d p 1 d = p 2 d = p 3 d = p 4 d = p 5 d = p 6 d

13. 13 9/7/00 Rent’s Parameter for Architecture1 u Segmentation = 1, channel width = 7, Pa = 0.62 Results

14. 14 9/7/00 Rent’s parameter for Architecture2 u Segmentation = 2, channel width = 7, Pa = 0.64

15. 15 9/7/00 Routing Utilization for seg = 1 u MVPR produces better routing utilization: s 15-25% better

16. 16 9/7/00 Routing Utilization for seg = 1:2 u MVPR produces better routing utilization: s 10-15% better

17. 17 9/7/00 Routing Utilization for seg = 2 u MVPR produces only minimally better routing utilization: s 1-5% better

18. 18 9/7/00 Routing Overhead Results (MVPR vs VPR) seg = 1 u results follow trend for changes in architecture

19. 19 9/7/00 CLB Area Utilization (MVPR v/s VPR) seg = 1 u results follow trend for changes in architecture u logic area utilization falls with increasing Pd

20. 20 9/7/00 MVPR over VPR for gnl generated ckts  25% higher RRU  10-15% lower Area

21. 21 9/7/00 Minimum Tracks Required on ISCAS Ckts

22. 22 9/7/00 MVPR over VPR for ISCAS ckts  same track utilization  5% lower average wire length  2-5% higher RRU  10-15% higher Area

23. 23 9/7/00 Conclusions u Pluses s New Cost Function s Minimum size fabric derived for Pd > Pa s Min-Area Max-RRU u Minuses s Errors in the estimation of Pd and Pa t second-order effects s Non-uniform interconnect complexities

24. 24 9/7/00 Future Work u Modifying MVPR s non-uniform interconnect complexity u timing/power-dissipation and complexity-aware FPGA placement u correlating track segmentation with accurate estimation of Rent’s parameter