1. Verilog to Routing CAD Tool Optimization
Yue Zha
Department of Electrical and Computer Engineering
University of Wisconsin Madison

2. Background Crossbar-based reconfigurable architecture
Tiles can be configured to implement logic and routing

3. Background CAD framework for mapping applications Verilog Parser
Technology mapper
Placer and Router

4. Motivation Long processing time, high cost
Few long distance interconnections
Route through more than 5 tiles
Fewer than 10%, on average
Logically partition the architecture
Divide the complex problem into multiple simple problems

5. Implementation Implement the Placer and Router in three parts
Group logic gates into clusters
Simulated annealing algorithm
Minimize inter-cluster interconnect
Evenly distribute logic gates among clusters
Local Placer and Router
Reuse the P&R tool in the original framework
Global Placer and Router (not completed)

6. Experimental Setup MCNC benchmark suite
Original CAD framework as the baseline
Sequential mode (one core) and parallel mode (four cores)
All CAD tool sets run on the same system
Core i7 and 8GB DDR3 memory

7. Experimental Results

8. Experimental Results

9. Questions?