Presentation is loading. Please wait.

Presentation is loading. Please wait.

Express Cube Topologies for On-chip Interconnects Boris Grot J. Hestness, S. W. Keckler, O. Mutlu † The University of Texas at Austin † Carnegie Mellon.

Published byEmil Singleton Modified over 8 years ago

Similar presentations

Presentation on theme: "Express Cube Topologies for On-chip Interconnects Boris Grot J. Hestness, S. W. Keckler, O. Mutlu † The University of Texas at Austin † Carnegie Mellon."— Presentation transcript:

1 Express Cube Topologies for On-chip Interconnects Boris Grot J. Hestness, S. W. Keckler, O. Mutlu † The University of Texas at Austin † Carnegie Mellon University ‡ Part of this work was performed at Microsoft Research Feb 17, 2009HPCA ‘09

2 The Era of Many-core UTCS2HPCA ‘09 Intel Larrabee 16+ cores Bidirectional ring interconnect UT TRIPS 2x16 exec tiles 16 NUCA tiles Multiple networks Intel Polaris 80 tiles 8x10 mesh Tilera Tile 64 cores 5 mesh networks

3 Networks on a Chip (NOCs)  On-chip advantages No pin constraints Rich wiring resources  On-chip limitations 2D substrates limit implementable topologies Logic area constrains use of wiring resources Energy/power budget caps  Focus Topologies for tomorrow’s many-core CMPs HPCA ‘093UTCS

4 Outline  Introduction  Existing topologies  Multidrop Express Channels (MECS)  Evaluation  Generalized Express Cubes  Summary UTCS4HPCA '09

5 UTCS5HPCA '09 2-D Mesh

6  Pros Low design & layout complexity Simple, fast routers  Cons Large diameter Energy & latency impact UTCS6HPCA '09 2-D Mesh

7  Pros Multiple terminals attached to a router node Fast nearest-neighbor communication via the crossbar Hop count reduction proportional to concentration degree  Cons Benefits limited by crossbar complexity UTCS7HPCA '09 Concentration (Balfour & Dally, ICS ‘06 )

8 UTCS8HPCA '09 Concentration  Side-effects Fewer channels Greater channel width

9 UTCS9HPCA ‘09 Replication CMesh-X2  Benefits Restores bisection channel count Restores channel width Reduced crossbar complexity

10 UTCS10HPCA '09 Flattened Butterfly (Kim et al., Micro ‘07)  Objectives: Improve connectivity Exploit the wire budget

11 UTCS11HPCA '09 Flattened Butterfly (Kim et al., Micro ‘07)

12 UTCS12HPCA '09 Flattened Butterfly (Kim et al., Micro ‘07)

13 UTCS13HPCA '09 Flattened Butterfly (Kim et al., Micro ‘07)

14 UTCS14HPCA '09 Flattened Butterfly (Kim et al., Micro ‘07)

15  Pros Excellent connectivity Low diameter: 2 hops  Cons High channel count: k 2 /2 per row/column Low channel utilization Increased control (arbitration) complexity UTCS15HPCA '09 Flattened Butterfly (Kim et al., Micro ‘07)

16 UTCS16HPCA '09 Multidrop Express Channels (MECS)  Objectives: Connectivity More scalable channel count Better channel utilization

17 UTCS17HPCA '09 Multidrop Express Channels (MECS)

18 UTCS18HPCA '09 Multidrop Express Channels (MECS)

19 UTCS19HPCA '09 Multidrop Express Channels (MECS)

20 UTCS20HPCA '09 Multidrop Express Channels (MECS)

21 UTCS21HPCA ‘09 Multidrop Express Channels (MECS)

22  Pros One-to-many topology Low diameter: 2 hops k channels row/column Asymmetric  Cons Asymmetric Increased control (arbitration) complexity UTCS22HPCA ‘09 Multidrop Express Channels (MECS)

23 Analytical Comparison UTCS23HPCA '09 CMeshFBflyMECS Network Size 642566425664256 Radix (conctr’d) 484848 Diameter 6142222 Channel count 2283248 Channel width 576115214472288 Router inputs 446146 Router outputs 4461444

24 Experimental Methodology TopologiesMesh, CMesh, CMesh-X2, FBFly, MECS, MECS-X2 Network sizes64 & 256 terminals RoutingDOR, adaptive Messages64 & 576 bits Synthetic trafficUniform random, bit complement, transpose, self-similar PARSEC benchmarks Blackscholes, Bodytrack, Canneal, Ferret, Fluidanimate, Freqmine, Vip, x264 Full-system configM5 simulator, Alpha ISA, 64 OOO cores Energy evaluationOrion + CACTI 6 UTCS24HPCA '09

25 UTCS25HPCA '09 64 nodes: Uniform Random

26 UTCS26HPCA '09 256 nodes: Uniform Random

27 UTCS27HPCA '09 Energy (100K pkts, Uniform Random)

28 UTCS28HPCA '09 64 Nodes: PARSEC

29 Generalized Express Cubes  Low-dimensional k-ary n-cube n = {1,2} Good fit for planar silicon  Express channels Improve connectivity MECS for better wire utilization  Multiple networks Improve throughput Reduce crossbar area & energy overhead  Hierarchical scaling UTCS29HPCA '09

30 Partitioning: a GEC Example UTCS30HPCA '09 MECS MECS-X2 Flattened Butterfly Partitioned MECS

31 Summary  MECS A novel one-to-many topology Good fit for planar substrates Excellent connectivity Effective wire utilization  Generalized Express Cubes Framework & taxonomy for NOC topologies Extension of the k-ary n-cube model Useful for understanding and exploring on-chip interconnect options Future: expand & formalize UTCS31HPCA '09

32 Summary  MECS A novel one-to-many topology Good fit for planar substrates Excellent connectivity Effective wire utilization  Generalized Express Cubes Framework & taxonomy for NOC topologies Extension of the k-ary n-cube model Useful for understanding and exploring on-chip interconnect options Future: expand & formalize UTCS32HPCA '09

33 UTCS33HPCA '09

Download ppt "Express Cube Topologies for On-chip Interconnects Boris Grot J. Hestness, S. W. Keckler, O. Mutlu † The University of Texas at Austin † Carnegie Mellon."

Similar presentations

A Novel 3D Layer-Multiplexed On-Chip Network

A Novel 3D Layer-Multiplexed On-Chip Network
The Locality-Aware Adaptive Cache Coherence Protocol George Kurian 1, Omer Khan 2, Srini Devadas 1 1 Massachusetts Institute of Technology 2 University.

The Locality-Aware Adaptive Cache Coherence Protocol George Kurian 1, Omer Khan 2, Srini Devadas 1 1 Massachusetts Institute of Technology 2 University.
Flattened Butterfly Topology for On-Chip Networks John Kim, James Balfour, and William J. Dally Presented by Jun Pang.

Flattened Butterfly Topology for On-Chip Networks John Kim, James Balfour, and William J. Dally Presented by Jun Pang.
Interconnection Networks: Topology and Routing Natalie EnrightJerger.

Interconnection Networks: Topology and Routing Natalie EnrightJerger.
1 Advancing Supercomputer Performance Through Interconnection Topology Synthesis Yi Zhu, Michael Taylor, Scott B. Baden and Chung-Kuan Cheng Department.

1 Advancing Supercomputer Performance Through Interconnection Topology Synthesis Yi Zhu, Michael Taylor, Scott B. Baden and Chung-Kuan Cheng Department.
Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks ______________________________ John Kim, William J. Dally &Dennis Abts Presented.

Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks ______________________________ John Kim, William J. Dally &Dennis Abts Presented.
CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips CiprianSeiculescu Stavros Volos Naser Khosro Pour Babak Falsafi Giovanni De Micheli.

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips CiprianSeiculescu Stavros Volos Naser Khosro Pour Babak Falsafi Giovanni De Micheli.
Kilo-NOC: A Network-on-Chip Architecture for Scalability and Service Guarantees Boris Grot The University of Texas at Austin.

Kilo-NOC: A Network-on-Chip Architecture for Scalability and Service Guarantees Boris Grot The University of Texas at Austin.
Allocator Implementations for Network-on-Chip Routers Daniel U. Becker and William J. Dally Concurrent VLSI Architecture Group Stanford University.

Allocator Implementations for Network-on-Chip Routers Daniel U. Becker and William J. Dally Concurrent VLSI Architecture Group Stanford University.
Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks Kapre et. al RC Reading Group – 3/29/2006 Presenter: Ilya Tabakh.

Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks Kapre et. al RC Reading Group – 3/29/2006 Presenter: Ilya Tabakh.
1 Lecture 23: Interconnection Networks Topics: communication latency, centralized and decentralized switches (Appendix E)

1 Lecture 23: Interconnection Networks Topics: communication latency, centralized and decentralized switches (Appendix E)
L2 to Off-Chip Memory Interconnects for CMPs Presented by Allen Lee CS258 Spring 2008 May 14, 2008.

L2 to Off-Chip Memory Interconnects for CMPs Presented by Allen Lee CS258 Spring 2008 May 14, 2008.
Firefly: Illuminating Future Network-on-Chip with Nanophotonics Yan Pan, Prabhat Kumar, John Kim †, Gokhan Memik, Yu Zhang, Alok Choudhary EECS Department.

Firefly: Illuminating Future Network-on-Chip with Nanophotonics Yan Pan, Prabhat Kumar, John Kim †, Gokhan Memik, Yu Zhang, Alok Choudhary EECS Department.
IP I/O Memory Hard Disk Single Core IP I/O Memory Hard Disk IP Bus Multi-Core IP R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Networks.

IP I/O Memory Hard Disk Single Core IP I/O Memory Hard Disk IP Bus Multi-Core IP R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Networks.
Lei Wang, Yuho Jin, Hyungjun Kim and Eun Jung Kim

Lei Wang, Yuho Jin, Hyungjun Kim and Eun Jung Kim
Design of a High-Throughput Distributed Shared-Buffer NoC Router

Design of a High-Throughput Distributed Shared-Buffer NoC Router
Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks Aniruddha N. Udipi with Naveen Muralimanohar*, Rajeev Balasubramonian University of Utah.

Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks Aniruddha N. Udipi with Naveen Muralimanohar*, Rajeev Balasubramonian University of Utah.
Interconnection Network Topology Design Trade-offs

Interconnection Network Topology Design Trade-offs
Orion: A Power-Performance Simulator for Interconnection Networks Presented by: Ilya Tabakh RC Reading Group4/19/2006.

Orion: A Power-Performance Simulator for Interconnection Networks Presented by: Ilya Tabakh RC Reading Group4/19/2006.
1 Lecture 21: Coherence and Interconnection Networks Papers: Flexible Snooping: Adaptive Filtering and Forwarding in Embedded Ring Multiprocessors, UIUC,

1 Lecture 21: Coherence and Interconnection Networks Papers: Flexible Snooping: Adaptive Filtering and Forwarding in Embedded Ring Multiprocessors, UIUC,

Similar presentations

Ads by Google